A new pipelined time-division multiplexing optical bus for implementing a linear-array parallel computer architecture is proposed. In this system, switches are introduced on the receiving segment of the bus to control the signal delays on the optical waveguide. The states of switches are dynamically programmable under the control of processors according to computation needs. In conjunction with coincident pulse processor addressing technique, the reconfigurability of signal delays becomes an integral part of parallel computation, as demonstrated by parallel algorithm design examples. The linear processor arrays based on such buses can be used as building blocks to construct parallel architectures of higher dimensions to achieve improved scalability and performance.