1 May 2004 Development of a general purpose configurable architecture for smart-pixel research
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Optical Engineering, 43(5), (2004). doi:10.1117/1.1689333
Abstract
The ever-increasing demand for communication bandwidth and system interconnectivity has been a motivating factor behind the integration of optoelectronics devices and conventional data processing circuitry. Based on the smart-pixel architectures first developed in the last decade, the architecture presented here monolithically integrates optical sensors with silicon CMOS-based circuitry to produce a generically programmable smart-pixel array. Two generations of the architecture are described and compared. We have proposed a reconfigurable photonic information-processing chip based on photonic VLSI device technology. Integrating detectors into a SIMD array removes the bottleneck associated with fetching slices of data. By fabricating the detectors along with logic circuits in a bulk CMOS process, the cost is minimized. The modular nature of the array organization facilitates replication of the configurable architecture for smart-pixel research (CASPR) concept into large arrays without a significant increase in design overhead. Thus, the CASPR architecture can provide the maximum flexibility associated with a reconfigurable smart-pixel array. Finally, we implement two design iterations of the CASPR architecture and show how the architecture might be used in a page-oriented optical data processing application.
Prosenjit Mal, Arvind Chokhani, V-Sathya Vagheeswar, Shankhar Raman Krishna Kumar, Jason Frederick Cantin, Fred Richard Beyette, "Development of a general purpose configurable architecture for smart-pixel research," Optical Engineering 43(5), (1 May 2004). http://dx.doi.org/10.1117/1.1689333
JOURNAL ARTICLE
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KEYWORDS
Data processing

Data storage

Logic

Data communications

Computer architecture

Optical communications

Photodetectors

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