1 October 2005 Comparison between electrical and optical global clock distributions for CMOS integrated circuits
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CMOS technology downscaling is expected to encounter a metallic interconnect bottleneck in the near future due to increasing delays of global on-chip interconnects, signal distortion, and timing uncertainty (skew and jitter), as well as power consumption. Silicon-compatible integration of optical on-chip interconnects is presented as an alternative solution. Integrated optics using silicon-on-insulator single-mode waveguides, Si-based modulators, and Ge photodetectors offers a feasible way to distribute the global clock over the whole chip. Taking into account the photodetectors' characteristics, with a CMOS-inverter-based transimpedance front-end amplifier and additional gain stages to ensure sufficient voltage swing, the performance of optical global clock distributions is compared with that of their metallic counterparts. The main advantages brought by optics include signal propagation with negligible distortion over centimeter-long distances (pulse spreading <1% of the clock period at a frequency of 100 GHz), reduction of skew and jitter in comparison with electrical repeater lines (optical skew/jitter <3% to 4% at a frequency of 50 GHz), lower sensitivity to temperature variations (optical delay variation <1.8% for a 100-K variation), and reduction of the total chip power consumption (negligible power consumption for the global clock distribution: <70 mW).
© (2005) Society of Photo-Optical Instrumentation Engineers (SPIE)
Eric Cassan, Eric Cassan, Delphine Marris-Morini, Delphine Marris-Morini, Mathieu Rouvière, Mathieu Rouvière, Laurent Vivien, Laurent Vivien, Suzanne C. Laval, Suzanne C. Laval, } "Comparison between electrical and optical global clock distributions for CMOS integrated circuits," Optical Engineering 44(10), 105402 (1 October 2005). https://doi.org/10.1117/1.2113127 . Submission:

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