1 June 2010 New fully digital programmable gain amplifier scheme with reduced clipping noise for complementary metal oxide semiconductor image sensor
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Abstract
We propose a fully digital programmable gain amplifier scheme that overcomes the clipped noise analog-to-digital converter (ADC) for complementary metal-oxide semiconductor (CMOS) image sensors. Adopting the new digital programmable gain amplifier (DPGA) scheme, it obtains low noise and low power usage, has a small size, and high robust gain characteristic. To reduce the clipping noise, one new current controling the reference voltage of a 9-bit flash ADC is brought about in this work. Using the fully digital amplification scheme with reduced clipping noise ADC solves almost all the problems of the conventional analog programmable gain amplifier (APGA) scheme, which has large noise, large power, and big chip size due to APGA, and two analog autozero loop (both clamping circuit loop and offset correction loop) circuits. Based on a 0.18-µm CMOS image sensor process, one product of video graphic array (VGA) format CMOS image sensor is fabricated. The silicon test shows a 68-dB dynamic range with the power consumption of 80 mW at 24 MHz and the total noise of about 2 mV (at 30 fps and 27 deg).
© (2010) Society of Photo-Optical Instrumentation Engineers (SPIE)
Xiangliang Jin, Zhibi Liu, "New fully digital programmable gain amplifier scheme with reduced clipping noise for complementary metal oxide semiconductor image sensor," Optical Engineering 49(6), 063203 (1 June 2010). https://doi.org/10.1117/1.3456706 . Submission:
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