1 September 2010 Design of butterfly-fat-tree optical network on-chip
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Abstract
The optical network on-chip is a popular option due to its low latency and high bandwidth with significantly lower power dissipation. A butterfly-fat-tree based optical network on-chip (BONoC) is designed with new optical router architecture. A hybrid signaling scheme is designed with the control information transferred and processed in the electronic domain. An energy efficient routing is proposed by considering the power consumption of the microresonators and signaling progress. Evaluation of the new optical butterfly-fat-tree NoC is made in three aspects-energy, latency, and throughput. The comparison of power consumption with its electronic counterpart shows that 64-core ONoC can save about 78.6% energy when compared to an electronic one of the same size. Finally, we simulate butterfly-fat-tree ONoC, and show the end-to-end delay and throughput with different traffic loads and various packet sizes.
© (2010) Society of Photo-Optical Instrumentation Engineers (SPIE)
Huaxi Gu, Shiqing Wang, Yintang Yang, Jiang Xu, "Design of butterfly-fat-tree optical network on-chip," Optical Engineering 49(9), 095402 (1 September 2010). https://doi.org/10.1117/1.3487749 . Submission:
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