20 April 2012 The demonstration of 10  Gbit/s time division multiplexing and 2.5  Gchip/s quasi-synchronous electrical code division multiplexing access passive optical network prototype system
Author Affiliations +
Optical Engineering, 51(4), 040507 (2012). doi:10.1117/1.OE.51.4.040507
Abstract
The authors propose a novel architecture of passive optical network (PON), which consists of time division multiplexing (TDM) based downstream (10  Gbit/s) and quasi-synchronization (Q-S) electrical code division multiplexing access (ECDMA) based upstream (2.5  Gchip/s), and realize the prototype of this TDM-ECDMA PON. The high speed (2.5  Gchip/s) all digital en/decoding of upstream have been achieved by field-programmable gate array in this prototype. The frames error rate (FER) free transmission of Q-S ECDMA based upstream is demonstrated after 20 km fiber link. Then receiver sensitivity of optical line terminal in upstream transmission can be improved ∼ 6  dB by coding gain compared with traditional 2.5  Gbit/s TDM PON.
Liang, Wang, Cao, Wang, Han, Wang, and Chen: The demonstration of 10  Gbit/s time division multiplexing and 2.5  Gchip/s quasi-synchronous electrical code division multiplexing access passive optical network prototype system

1.

Introduction

PON is the most attractive optical access network solution in terms of cost effectiveness. Currently, TDM-based PON (EPON and GPON) is widely deployed. Recently, ECDM as multiplexing technology for PON downstream was proposed and demonstrated,12.3 in which the electrical CDM en/decoding were, respectively, realized in digital/analog methods or offline processing on computer. The coexistence of ECDM with other technology was also proposed. The architecture of TDM-PON coexisting with synchronous ECDM-PON by coupler was demonstrated in Ref. 4, and this architecture’s ECDM en/decoding used same methods with Refs. 1 and 2. All these ECDM PON demonstrations focused on experimental PON downstream and realized synchronization in experimental methods by equipment.

In this paper, the TDM-ECDMA PON system has firstly been proposed, in which ECDMA and TDM have been, respectively, employed in upstream and downstream as access and multiplexing technology. Moreover, we have realized the prototype of TDM-ECDMA PON. The high speed (2.5Gchip/s) en/decoding of upstream are carried out by real time pipelined processing based on field-programmable gate array (FPGA) in this prototype. The digital en/decoding can lead to this system being controllable and flexible. A new fiber channel suited synchronization mechanism is designed to maintain the Q-S of the prototype upstream. In EDMA-based upstream of the prototype, the optical line terminal (OLT) receiver sensitivity can be improved by coding gain, which has been analyzed in Ref. 5 and multiple-access interference (MAI) can be reduced by synchronization mechanism.

2.

Architecture of TDM-ECDMA PON System

The proposed TDM-ECDMA PON system is shown in Fig. 1. Downstream and upstream, respectively, work at 1550/1270nm wavelengths. In upstream, the optical network unit’s (ONU’s) data are en/decoded at ONU and OLT, respectively. The upstream need to realize two major types of synchronizations as the following: synchronization between encoding codes and OLT’s local decoding codes to guarantee correct decoding; synchronization between different accessed ONUs to reduce MAI. These two synchronous precision can distribute in a fixed small-rang though by the new synchronization mechanism. Therefore, the PON’s upstream includes data transmitting and synchronization works status.

Fig. 1

Architecture of TDM-ECDMAPON.

OE_51_4_040507_f001.png

At data transmitting status, each accessed ONU transmits 2.5Gchip/s encoding data, which are temporally encoded by the FPGA-based encoder module with 32-bit length Walsh codes. The splitter outputs are multi-level signals because adding different ONUs signals. At the OLT, the upstream data will be decoded by FPGA’s decoder module after avalanche photodiode (APD) based O/E and 5Gsamples/s analog to digital converter (ADC). The coding gain is the most important factor that can improve OLT’s receiver sensitivity.

The synchronization mechanism is supported by synchronous acquisition and processing modules in OLT and ONU, respectively. The ONU’s 10 G PHY can recover the OLT’s clock signals from downstream data to make ONU and OLT at the same clock domain, which is the foundation of the synchronization mechanism. The synchronization status ONU transmits 2.5Gbit/s 31-bit length PN sequences, which have good auto-correlation. At OLT, the FPGA’s synchronous acquisition module acquires the information of synchronous phase, which appears with the highest auto-correlation peak. According to the results of acquisition, the OLT generates synchronization frames that contain the information of time delay about synchronization status ONU, and OLT’s downstream data transmitter module can multiplex the frames with 10Gbit/s downstream data by TDM method. The synchronization status ONU’s downstream data receiver module can extract the synchronization frames from downstream data and forward them to FPGA’s synchronization processing module. According the synchronization frames the controllable delay and FPGA’s delay adjuster of this ONU are used to adjust 0.5Tc(0.2ns) and an integer multiple of Tc(0.4ns) time delay, respectively. The synchronous mechanism can maintain Q-S precision at (0.5Tc, 0.5Tc) between ONU’s encoding and OLT’s decoding codes.

The synchronization mechanism indirectly keeps Q-S between different ONUs’ outputs because different accessed ONUs maintain Q-S with OLT. The relative time delays of any two accessed ONUs’ outputs distribute in (Tc, Tc) that obviously reduces the ECDMA-PON upstream MAI to promote signal to noise ratio because MAI decreases with the degree of synchronization increasing.6

3.

Experiment Setup and Results

Figure 2 shows the TDM-ECDMA PON experiment setup. In this experiment, we mainly focus on the performance of the upstream. As shown in Fig. 3(a), the splitter outputs are four-level waveform, and the encoded chip rate is 2.5Gchip/s. In upstream, the 78.125Mbit/s user data (Ethernet frames) of three ONUs are generated by the data quality analyzer (DQA). The relationship between chip rate and data rate after encoding as: chip rate=data rate×code length. The variable optical attenuator (VOA) controls the OLT receiving optical power. After being decoded and framed, the OLT transmits upstream Ethernet frames to DQA, which counts the mean FER of three ONUs.

Fig. 2

The experiment setup, the prototype of OLT and ONU.

OE_51_4_040507_f002.png

Fig. 3

(a) Four-level waveform of prototype upstream (b) 20 km fiber transmission FER measurements of TDM-PON and ECDM-PON.

OE_51_4_040507_f003.png

In this experiment, TDM-PON is a point-to-point 2.5Gbit/s on-off keying based system. Figure 3(b) depicts the FER performance of the TDM-ECDMA PON upstream and TDM-PON, respectively. On average, each frame contains 103 bit, so the 106 FER roughly equals 109 BER. The results show coding gain can improve TDM-ECDMA upstream sensitivity 6dB. The experimental results of improvement are less than the theoretical value (7.5 dB)5 in a zero MAI synchronous system because the MAI still exists in Q-S system. However, the Q-S system can guarantee the obvious improvement of sensitivity by decreasing MAI. According to ONU’s 2dBm transmitting optical power and OLT’s 36dBm sensitivity, the 1:256 splitting ratio which insertion loss is 24dB, can be supported by this system.

4.

Conclusion

The proposed architecture of TDM-ECDMA PON system has been demonstrated successfully. In ECDMA based upstream, the digital pipeline processing based high speed en/decoding has been realized. Moreover, the novel fiber channel suited synchronization mechanism has been verified in the experiment. The 6dB improvement of upstream receiver sensitivity can support longer transmission and a quadruple splitting ratio. The proposed architecture could be one of competitive solutions for the next generation of PON (NGPON).

Acknowledgments

This study is supported by the National High Technology Research and Development Program of China (No. 2011AA01A104) and the Beijing Science and Technology Program (No. D111101001511001)

References

1. 

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2. 

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6. 

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Siyuan Liang, Liqian Wang, Yingying Cao, Zhen Wang, Yamei Han, Dao Wang, Xue Chen, "The demonstration of 10  Gbit/s time division multiplexing and 2.5  Gchip/s quasi-synchronous electrical code division multiplexing access passive optical network prototype system," Optical Engineering 51(4), 040507 (20 April 2012). http://dx.doi.org/10.1117/1.OE.51.4.040507
Submission: Received ; Accepted
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KEYWORDS
Prototyping

Time division multiplexing

Code division multiplexing

Field programmable gate arrays

Passive optical networks

Receivers

Computer programming

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