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An approach was presented to fabricate wafer-scale nanoring structures based on nanopillar array templates fabricated by nanoimprint lithography. This fabrication method combined UV-curing nanolithography technology, metal deposition, and an etching process, which made it possible to tune the geometric properties of nanorings: height, diameter, and linewidth for various materials, such as Au and Ni. Nanoring arrays showed potential applications in many fields, including memory storage, biosensing, and optical devices. The optical measurement of Au nanorings (d=380  nm) showed its strong transmission resonances at the wavelength of 2.1  μm. A modified version of this fabrication method by depositing Ni in a controlled angle as a sacrificial layer was also utilized to create nanocrescent arrays. This modified method could easily tune the width of crescents through the nickel deposition angles and nanopillar template heights. The large-area gold nanocrescent arrays showed strong polarization-dependent transmission bands. Plasmonic crescent structures were expected to apply in infrared metamaterial and chemical sensing.

As extreme ultraviolet lithography becomes closer to reality for high volume production, its peculiar modeling challenges related to both inter and intrafield effects have necessitated building an optical proximity correction (OPC) infrastructure that operates with field position dependency. Previous state-of-the-art approaches to modeling field dependency used piecewise constant models where static input models are assigned to specific x/y-positions within the field. OPC and simulation could assign the proper static model based on simulation-level placement. However, in the realm of 7 and 5 nm feature sizes, small discontinuities in OPC from piecewise constant model changes can cause unacceptable levels of edge placement errors. The introduction of dynamic model generation (DMG) can be shown to effectively avoid these dislocations by providing unique mask and optical models per simulation region, allowing a near continuum of models through the field. DMG allows unique models for electromagnetic field, apodization, aberrations, etc. to vary through the entire field and provides a capability to precisely and accurately model systematic field signatures.

Graphoepitaxy directed self-assembly is a potential low-cost solution for patterning via layers with pitches beyond the reach of a single optical lithographic exposure. In this process, selective control of the interfacial energy at the bottom and sidewall of the template is an important but challenging exercise. A dual brush process is implemented, in which two brushes with distinct end-groups are consecutively grafted to the prepattern to achieve fully independent modification of the bottom and sidewall surface of the template. A comprehensive study of hole pattern quality shows that using a dual brush process leads to a substantial improvement in terms of positional and dimensional variability across the process window. These findings will be useful to others who wish to manipulate polymer–surface interactions in directed self-assembly flows.

With the advancement of very large scale integrated circuits (VLSI) technology nodes, lithographic hotspots become a serious problem that affects manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with the extreme scaling of transistor feature size and layout patterns growing in complexity, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. We present a deep convolutional neural network (CNN) that targets representative feature learning in lithography hotspot detection. We carefully analyze the impact and effectiveness of different CNN hyperparameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always in the minority in VLSI mask design, the training dataset is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from a high number of false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply hotspot upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

With the shrinking of critical dimension, the demand for a process window has reached a new level, which is denoted as the depth of focus at certain exposure latitudes. Therefore, high-quality monitoring and controlling of focus shift are becoming more and more critical. With the purpose of providing an optimal focus monitoring mark, which can be applied in freeform or off-axis illumination with a big sigma and hypernumerical aperture (NA) scheme, a global optimization method combined with the idea of a genetic algorithm is developed. For illustration, two optimal mask structures under quasar and freeform illumination conditions are given by the optimized method. The numerical simulations with the lithography simulator PROLITH are provided to demonstrate the performances of these two structures. In addition, the robustness of these optimized structures is analyzed by considering the phase-shift error in mask manufacturing. The above simulation results verify the effectiveness and validity of the proposed optimization methodology and also show that the mask structure provided by the optimized method has the potential to be an efficient candidate for measuring the defocus of scanners in the immersion lithography with hyper NA.

Initial readiness of extreme ultraviolet (EUV) patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the “effective” k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30  nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Using a grafted polymer brush adhesion layer, we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush, and resist. We show printing of sub-36-nm pitch features with a good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight, and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.

Scanning laser lithography is a maskless method for exposing photoresist during semiconductor manufacturing. In this method, the energy of a focused beam is controlled while scanning the beam or substrate. With a positive photoresist material, areas that receive an exposure dosage over the threshold energy are dissolved during development. The surface dosage is related to the exposure profile by a convolution and nonlinear function, so the optimal exposure profile is nontrivial. A gradient-based optimization method for determining an optimal exposure profile, given the desired pattern and models of the beam profile and photochemistry, is described. This approach is more numerically efficient than optimal barrier-function-based methods but provides near-identical results. This is demonstrated through simulation and experimental lithography.

A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.

As the semiconductor technology node comes to 14 nm and below, using bright-field exposure with negative tone development (NTD) has been a dominant lithographic solution for metal and contact layers, which has benefits of larger process windows and higher image contrasts than positive tone development (PTD). For PTD, a resist model is usually optional in source mask optimization (SMO) because optical models with aerial image blur can predict resist behaviors in most cases. However, NTD has much stronger resist effects, such as resist shrinkage and two-dimensional-effect-induced local stress. It has been suggested that the calibrated resist model is strongly required in the SMO of NTD process. We clarify this issue—the necessity of resist model in SMO for NTD process. First, we analyze the mismatch between simulation and experimental data when the aerial image blur is only used to simulate resist effects. Second, we present the calibration flow of resist model. Finally, we use the calibrated resist model to check the test pattern and run the SMO. The result demonstrates that the simulation data have the same tendency with experimental data, and the model has a good prediction on NTD resist behaviors under different conditions.

We report on the extreme ultraviolet (EUV) patterning performance of tin-oxo cages. These cage molecules were already known to function as a negative tone photoresist for EUV radiation, but in this work, we significantly optimized their performance. Our results show that sensitivity and resolution are only meaningful photoresist parameters if the process conditions are optimized. We focus on contrast curves of the materials using large area EUV exposures and patterning of the cages using EUV interference lithography. It is shown that baking steps, such as postexposure baking, can significantly affect both the sensitivity and contrast in the open-frame experiments as well as the patterning experiments. A layer thickness increase reduced the necessary dose to induce a solubility change but decreased the patterning quality. The patterning experiments were affected by minor changes in processing conditions such as an increased rinsing time. In addition, we show that the anions of the cage can influence the sensitivity and quality of the patterning, probably through their effect on physical properties of the materials.

A simulation flow for laser direct-write lithography (LDWL), a maskless lithography process in which a focused laser beam is scanned through a photoresist, is proposed. The simulation flow includes focusing of Gaussian beams, photoresist exposure, free-radical polymerization chemistry of the photoresist, and photoresist development. We applied the simulation method to investigate the scaling of feature sizes or linewidths for a varying number of exposure cycles at a total constant exposure dose. Experimental results from literature demonstrate that exposing the photoresist over multiple exposure cycles causes a reduction in linewidths. We explore possible reasons for this phenomenon and conclude that radical losses occurring between subsequent exposures provide a possible explanation of the observed effects. Furthermore, we apply the developed simulation method to analyze lithographic structures that were fabricated by a combination of LDWL and nanoimprint lithography. The simulation results agree with the experimental tendencies of a reduced likelihood of overexposures with an increase in the number of exposure cycles.

Line-edge roughness (LER) has important impacts on the quality of semiconductor device performance, and power spectrum estimates are useful tools in characterizing it. These estimates are often obtained by taking measurements of many lines and averaging a classical power spectrum estimate from each one. While this approach reduces the uncertainty of the estimates, there are disadvantages to the collection of many measurements. We propose techniques with widespread application in other fields that simultaneously reduce data requirements and the uncertainty of LER power spectrum estimates over current approaches at the price of computational complexity. Multitaper spectral analysis uses an orthogonal collection of data windowing functions or tapers to obtain a set of approximately statistically independent spectrum estimates. The Welch overlapped segment averaging is an earlier approach to reduce the uncertainty of power spectrum estimates. There are known techniques to evaluate the uncertainty of power spectrum estimates. We simulate random rough lines using the Thorsos method.

We report our findings in developing a low-power etching recipe using a newly acquired reactive-ion etching (RIE) tool (RIE-10NR, Samco, Japan), with the aim of achieving smooth and vertical sidewalls in micropatterned silicon substrate. We used a combination of CF4, SF6, and O2 gases, which at low power (30 W) and low pressure (2 Pa) allowed for vertical silicon etching (aspect ratio ∼2). We used photoresist and silicon oxide as the etching masks. As it is a continuous etching process, scalloping effects were not present, which is contrary to the process done with an inductively coupled plasma-based “Bosch” approach. We also show a successful use of these microstructures as master mold in soft-lithographic techniques for producing devices in elastomeric materials that have applications in mechanobiology. To the best of our knowledge, the recipe we present here has the lowest combination of power and pressure for etching silicon with vertical profile using a standard, parallel plates RIE tool.

The parallel plate capacitive humidity sensor based on the grid upper electrode is considered to be a promising one in some fields which require a humidity sensor with better dynamic characteristics. To strengthen the structure and balance the electric charge of the grid upper electrode, a strip is needed. However, it is the strip that keeps the dynamic characteristics of the sensor from being further improved. The numerical method is time- and cost-saving, but the numerical study on the response time of the sensor is just of bits and pieces. The numerical models presented by these studies did not consider the porosity effect of the polymer film on the dynamic characteristics. To overcome the defect of the grid upper electrode, a new structure of the upper electrode is provided by this paper first, and then a model considering the porosity effects of the polymer film on the dynamic characteristics is presented and validated. Finally, with the help of software FLUENT, parameter effects on the response time of the humidity sensor based on the microhole upper electrode are studied by the numerical method. The numerical results show that the response time of the microhole upper electrode sensor is 86% better than that of the grid upper electrode sensor, the response time of humidity sensor can be improved by reducing the hole spacing, increasing the aperture, reducing film thickness, and reasonably enlarging the porosity of the film.

We report the nanofabrication and characterization of x-ray transmission gratings with a high aspect ratio and a feature size of down to 65 nm. Two nanofabrication methods, the combination of electron beam and optical lithography and the combination of electron beam, x-ray, and optical lithography, are presented in detail. In the former approach, the proximity effect of electron beam lithography based on a thin membrane of low-z material was investigated, and the x-ray transmission gratings with a line density of up to 6666  lines/mm were demonstrated. In the latter approach, which is suitable for low volume production, we investigated the x-ray mask pattern correction during the electron beam lithography process and the diffraction effect between the mask and wafer during the x-ray lithography process, and we demonstrated the precise control ability of line width and vertical side-wall profile. A large number of x-ray transmission gratings with a line density of 5000  lines/mm and Au absorber thickness of up to 580 nm were fabricated. The optical characterization results of the fabricated x-ray transmission gratings were given, suggesting that these two reliable approaches also promote the development of x-ray diffractive optical elements.

The infrared absorption of SF6 gas is narrowband and peaks at 10.6  μm. This narrowband absorption posts a stringent requirement on the corresponding sensors as they need to collect enough signal from this limited spectral bandwidth to maintain a high sensitivity. Resonator-quantum well infrared photodetectors (R-QWIPs) are the next generation of QWIP detectors that use resonances to increase the quantum efficiency for more efficient signal collection. Since the resonant approach is applicable to narrowband as well as broadband, it is particularly suitable for this application. We designed and fabricated R-QWIPs for SF6 gas detection. To achieve the expected performance, the detector geometry must be produced according to precise specifications. In particular, the height of the diffractive elements and the thickness of the active resonator must be uniform, and accurately realized to within 0.05  μm. Additionally, the substrates of the detectors must be completely removed to prevent the escape of unabsorbed light in the detectors. To achieve these specifications, two optimized inductively coupled plasma etching processes were developed. Due to submicron detector feature sizes and overlay tolerance, we used an advanced semiconductor material lithography stepper instead of a contact mask aligner to pattern wafers. Using these etching techniques and tool, we have fabricated focal plane arrays with 30-μm pixel pitch and 320×256 format. The initial test revealed promising results.

This research considers the problem of generating compact vector representations of physical design patterns for analytics purposes in semiconductor patterning domain. PatterNet uses a deep artificial neural network to learn mapping of physical design patterns to a compact Euclidean hyperspace. Distances among mapped patterns in this space correspond to dissimilarities among patterns defined at the time of the network training. Once the mapping network has been trained, PatterNet embeddings can be used as feature vectors with standard machine learning algorithms, and pattern search, comparison, and clustering become trivial problems. PatterNet is inspired by the concepts developed within the framework of generative adversarial networks as well as the FaceNet. Our method facilitates a deep neural network (DNN) to learn directly the compact representation by supplying it with pairs of design patterns and dissimilarity among these patterns defined by a user. In the simplest case, the dissimilarity is represented by an area of the XOR of two patterns. Important to realize that our PatterNet approach is very different to the methods developed for deep learning on image data. In contrast to “conventional” pictures, the patterns in the CAD world are the lists of polygon vertex coordinates. The method solely relies on the promise of deep learning to discover internal structure of the incoming data and learn its hierarchical representations. Artificial intelligence arising from the combination of PatterNet and clustering analysis very precisely follows intuition of patterning/optical proximity correction experts paving the way toward human-like and human-friendly engineering tools.

A capacitive tactile sensor comprising two capacitors was developed to enhance detection by more than doubling the spatial resolution. This arrangement reduced the number of required capacitors from four to two and reconfigured the capacitor shape from square to rectangular, resulting in a symmetric spatial resolution in the x- and y-directions. The theoretical evaluations, simulation predictions, device fabrication, and data analysis conducted in this study yielded identical results. In addition, angle detection errors resulting from fabrication and material uncertainties were comprehensively examined for the first time. The evaluations performed regarding the capacitor configuration further indicated that the sensitivity of shear force detection in this study was optimized with the requirement of a symmetric design.

The output of one typical capacitive microelectromechanical system (MEMS) accelerometer under square wave bias voltage is discussed. Output drift of the accelerometers should be suppressed to improve the device performance. Theoretical analysis indicates that square wave bias voltage can be applied instead of the DC bias voltage to mitigate the dielectric charging-induced output drift. Theoretical models of the sensing structure under square wave bias voltage indicate that both square wave and DC bias voltage can generate the same electrostatic force among the sensing structure. Therefore, the system equilibrium can be maintained with square wave bias voltage when the same input acceleration is applied. Configuration and the frequency of the square wave bias voltage are analyzed to maintain the system equilibrium and device function. Experimental results show that although the magnitude of the output voltage is slightly decreased, output drift can be significantly suppressed when the square wave voltage is applied.

This article corrects an error in the original publication.