As integrated circuit (IC) fabrication technologies become more complex, new and ever-shrinking metrology requirements are becoming increasingly challenging to achieve. Some examples of recently added complexity include the shift from planer to vertical devices and increased use of multipatterning to the future complexities that may come from characterizing nanowires and III-V materials. These complexities are stressing metrology’s capability to levels not encountered in the past and as a result conventional metrology approaches are having a hard time keeping up. Measurement uncertainty requirements are already at sub-nanometer levels and new three-dimensional metrology requirements necessitate measuring the critical dimension, thickness, and sidewall angle of a given critical structure.
In order to meet these challenges innovative thinking is required. Over the past several years, the metrology community has been embracing the concept that if a given measurement technology cannot meet all of the given requirements, then maybe using data from multiple metrology technologies and combining it in a clever way can provide a better end result. This is referred to as hybrid metrology. Additionally, since there are so many different metrology technologies existing today (likely many more choices than in any other sector, such as etch or lithography), how does one best leverage obtaining the best results given so many choices? Consideration of all possibilities, determining what technology to use when and whether it can be used alone or in tandem with other technologies, is called holistic metrology. Both of these concepts were combined to describe this special section. This is an ever-growing area of exploration in metrology and has many more facets than a single special issue can cover. All fourteen papers are related in some way to holistic/hybrid metrology with a particular focus on the use of unconventional approaches.
The paper from Vaid et al. presents work using the concept of co-optimization-based metrology hybridization. Hybrid co-optimization involves the combination of data from two or more metrology tools such that the output of each tool is improved by the output of the other tool using parallel regression. In this example the image analysis parameters from a critical dimension scanning electron microscope (CD-SEM) are modulated by the profile information from the optical critical dimension (OCD or scatterometry), while the OCD-extracted profile is concurrently optimized through addition of the CD-SEM CD results. The test wafer used was from the 14-nm node; it was a FinFET high-k/interfacial layer (HK/ILK) structure. The authors found when compared to the non-hybrid approach, the correlation to reference measurements of the HK layer thickness measurement using hybrid co-optimization resulted in an improvement in relative accuracy of about 40%. Additional results are presented in the paper.
The paper by Chen et al. introduces the concept of device-correlated metrology (DCM). This is a systematic approach to quantify and overcome the bias between target-based optical overlay results and device overlay values. This approach deals with one of the main issues in overlay metrology, which is accuracy—more specifically, determining the bias between the overlay target and the actual device. In order to quantify the bias components between target and device, they introduce a new hybrid target integrating an optical overlay target with a device mimicking CD-SEM target. This hybrid target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the optical and device target on the same layer after etch for all layers. The results show that for the process-compatible hybrid targets the bias between the optical and device target is small. Further there is good correlation between the CD-SEM and optical overlay tool measuring the same optical target. The authors found this correlation helps verify the accuracy of the optical measurements at certain conditions. Many additional interesting results are also present in this paper.
Abe et al. propose using an inline reference metrology system called the verification metrology system (VMS) to improve the robustness of the inline metrology tools. This system combines inline metrology and non-destructive reference metrology tools. VMS can detect the false alarm error and the nondetectable error caused by measurement robustness decay of inline metrology tools. Grazing incidence small-angle x-ray scattering (GI-SAXS) was selected as the inline reference metrology tool because of its high robustness capability for underlayer structural changes. VMS with scatterometry and GI-SAXS was evaluated for measurement robustness. The potential to detect metrology system errors was confirmed using VMS. Cost-reduction effect of VMS was estimated for the false alarm case. The authors determined that VMS was effective for total cost reduction with low sampling which was optimized based on process qualities.
Le Cunff et al. performed a study to evaluate the benefits of combining techniques to improve the overall metrology of thin silicon germanium (SiGe) epitaxial layers doped with boron. A specifically designed set of wafers was processed and measured by different in-line metrology tools and characterization techniques. The paper describes the best strategy for combining metrology techniques in order to reliably determine dopant concentration and Ge composition measurement of the layers. It demonstrates that hybrid metrology enables key improvements in manufacturing and engineering environments.
We hope you enjoy this collection of articles.
Alok Vaid is manager of the optical metrology group at GlobalFoundries Fab8 Malta, NY. He also owns strategic metrology planning and roadmap for GlobalFoundries. He has been working in the area of metrology research, development, and manufacturing for more than a decade and has published several scientific papers (∼50) in various conference proceedings and journals. He received a master’s degree in mechanical engineering from the University of Texas at Austin and a bachelor’s degree in manufacturing engineering from the University of Delhi. He is a recipient of the Diana Nyyssonen Memorial Award for the Best Paper at 2008 SPIE conference. He is currently serving as a committee member at SPIE and IEEE/ASMC conferences.
Eric Solecky is a senior metrology lead for IBM’s 300 mm Manufacturing Facility in East Fishkill, NY, and is currently on assignment at GlobalFoundries Fab8 Malta, NY. He has been working in the area of metrology development and manufacturing for over 15 years, covering various areas with a particular emphasis on CDSEMs. He has published several scientific papers (over 30) in various conference proceeding and journals. He also holds over 20 patents. Eric received his master’s degree in microelectronics from Rensselaer Polytechnic Institute and a bachelor’s degree in microelectronics from Rochester Institute of Technology. He is currently serving as a committee member at SPIE.