An emerging trend within the microfluidic community is to standardize common parts in order to facilitate design and production activities. The goal is clear: to enhance interoperability and promote plug-and-play. A recent launch of a pan-European project, Microfluidic (MF) Manufacturing, has identified an item that is in immediate need of standardization: having in place geometrical specifications for MF connectors. In order to accelerate the adoption of such standards, there is a need to consider the pivotal role of standard documents. The purpose of this paper is to provide background information on document standards development. In addition, the future implications related to the MF manufacturing project will be discussed. A strengths, weaknesses, opportunities, and threats analysis has been carried out to identify points of action. The findings show that although there is a need to publish under International Organization for Standardization (ISO), the actual realization of a full ISO standard document is not feasible. The recommendation is to initially publish via an ISO Workshop Agreement. Parallel to such activity, there is a need to encourage stakeholders help kick start a currently dormant working group that supports microfluidics under ISO to help pave the way for future standardization activities in the microfluidics community.

Patterned mask inspection for an etched multilayer (ML) extreme ultraviolet mask was investigated. In order to optimize the mask structure from the standpoint of a pattern inspection the mask structure not only from the standpoint of a pattern inspection by using a projection electron microscope but also by using a projection electron microscope but also by considering the other fabrication processes using electron beam techniques such as critical dimension metrology and mask repair, we employed a conductive layer between the ML and substrate. By measuring the secondary electron emission coefficients of the candidate materials for the conductive layer, we evaluated the image contrast and the influence of the charging effect. In the cases of 40-pair ML, 16-nm-sized extrusion and intrusion defects were found to be detectable more than 10 sigma in half pitch 44, 40, and 32 nm line-and-space patterns. Reducing 40-pair ML to 20-pair ML degraded the image contrast and the defect detectability. However, by selecting B4C as a conductive layer, 16-nm-sized defects and etching residues remained detectable. The 16-nm-sized defects were also detected after the etched part was refilled with Si. A double-layer structure with 2.5-nm-thick B4C on metal film used as a conductive layer was found to have sufficient conductivity and also was found to be free from the surface charging effect and influence of native oxide.

The usage of an extreme ultraviolet (EUV) pellicle is regarded as a potential solution for defect control because it can protect the mask from airborne debris. However, some obstacles disrupt realistic application of the pellicle, such as its structural weakness, the risk of thermal damage, and so on. For these reasons, flawless fabrication of the pellicle is impossible. We discuss the influence of a deformed pellicle in terms of the nonuniform intensity distribution and the critical dimension (CD) uniformity. When we consider a 16-nm periodic pattern with dipole illumination, a transmission difference (max-min) of 0.7% causes CD uniformity of 0.1 nm. The deflection of the aerial image caused by gravity is small enough to ignore. CD uniformity is <0.1  nm, even for the current gap of 2 mm between the mask and pellicle. However, wrinkling of the EUV pellicle, caused by heat, can cause serious image distortion because a wrinkled EUV pellicle experiences both transmission loss variation as well as CD nonuniformity. The local angle of a wrinkle (as opposed to the period or amplitude of a wrinkle) is the main factor that influences CD uniformity, and a local angle of <∼16  deg is needed to achieve 0.1-nm CD uniformity for a 16-nm L/S pattern.

Native acting phase-programmed defects, otherwise known as buried program defects, with attributes very similar to native defects, were successfully fabricated using a high-accuracy overlay technique. The defect detectability and visibility were analyzed with conventional amplitude and phase-contrast blank inspection at 193-nm wavelength, pattern inspection at 193-nm wavelength, and scanning electron microscopy. The mask was also printed on wafer, and printability is discussed. Finally, the inspection sensitivity and wafer printability are compared, leading to the observation that the current blank- and pattern-inspection sensitivity is not enough to detect all of the printable defects.

Several challenges hinder extreme ultraviolet lithography (EUVL) photomask fabrication and its readiness for high-volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. By using known defect locations on a blank, the mask design can be intentionally shifted to avoid patterning directly over a defect. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7-nm technology node (N7). An empirical error budget to compensate for various measurement errors, based on the latest HVM inspection and write tool capabilities, is first established and then verified postpatterning. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed using fully functional N7 chip designs that were recently used to fabricate working silicon–germanium devices. Probability of defect-free masks are explored for various N7 photomask levels, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks and what is required to construct a complete defect-free EUV mask set.

Development of nanoimprint lithography (NIL) templates is discussed. The template fabrication process and its performance are presented with consideration of the requirements of NIL for high-volume manufacturing. Defectivity, image placement, and critical dimension uniformity are the three major performance parameters of the templates, and their current status is shown.

To evaluate defects on extreme ultraviolet (EUV) masks at the blank state of manufacturing, we developed a micro-coherent EUV scatterometry microscope (micro-CSM). The illumination source is coherent EUV light with a 140 nm focus diameter on the defect using a Fresnel zone plate. This system directly observes the reflection and diffraction signals from a phase defect. The phase and the intensity image of the defect are reconstructed with the diffraction images using ptychography, which is an algorithm of the coherent diffraction imaging. We observed programmed phase defect on a blank EUV mask. Phase distributions of these programmed defects were well reconstructed quantitatively. The micro-CSM is a very powerful tool to review an EUV phase defect.

Extreme ultraviolet lithography (EUVL) patterned mask defect detection is one of the major issues to overcome for realization of EUVL-based device fabrication. We have designed projection electron microscope (PEM) optics that have been integrated into a new inspection system called EBEYE-V30 (“Model EBEYE” is EBARA’s model code), and the PEM system performs well in half-pitch (hp) 16-nm node EUVL patterned mask inspection applications. We also discuss the extendibility of this system to 11-nm node defect detection. The progress made in the performance of the PEM optics is not simply about producing an image sensor with higher resolution but is also about improvement of the image processing to enhance the defect signal. A high-speed image sensor, a high-speed image-processing circuit, and a bright and stable electron source are necessary for hp 11-nm defect inspection. We describe the experimental results for EUVL patterned mask inspection using the above system for the hp 11-nm node. Programmed hp 11-nm defects (equivalent to 44 nm on the mask) are used for defect detection sensitivity evaluation. Defects as small as 16 nm on the mask could be detected using the current PEM system configuration.

Optical proximity correction (OPC) is one of the most important techniques in today’s optical lithography-based manufacturing process. Although the most widely used model-based OPC is expected to achieve highly accurate correction, it is also known to be extremely time-consuming. This paper proposes a regression model for OPC using a hierarchical Bayes model (HBM). The goal of the regression model is to reduce the number of iterations in model-based OPC. Our approach utilizes a Bayes inference technique to learn the optimal parameters from given data. All parameters are estimated by the Markov Chain Monte Carlo method. Experimental results show that utilizing HBM can achieve a better solution than other conventional models, e.g., linear regression-based model, or nonlinear regression-based model. In addition, our regression results can be used as the starting point of conventional model-based OPC, through which we are able to overcome the runtime bottleneck.

A variety of repairs were conducted on extreme ultraviolet (EUV) multilayer, including protection against pattern degradation in manufactural use, in order to evaluate feasibility of multilayer repair and subsequent protection schemes. The efficacy of postrepair protection techniques is evaluated to determine the lifetime of multilayer repairs. Simulations were used to select the optimal material thicknesses for repair protection, and the simulation results are verified with the lithographic results. The results showed a high correlation coefficient. Finally, all repaired sites were cleaned multiple times to quantify repair durability and impact on wafer critical dimension (CD). Aerial imaging of the repair sites before and after cleans showed a dramatic degradation of wafer CD. However, we show that applying a surface protection material after multilayer repair successfully mitigates the influence of multilayer degradation during extensive manufacturing operations.

In a previous work, we demonstrated that the current optical proximity correction model assuming the mask pattern to be analogous to the designed data is no longer valid. An extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason, an accurate mask model has been calibrated for a 14-nm logic gate level. A model with a total RMS of 1.38 nm at mask level was obtained. Two-dimensional structures, such as line-end shortening and corner rounding, were well predicted using scanning electron microscopy pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects, and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular.

The specifications for critical dimension (CD) accuracy and line edge roughness are getting tighter to promote every photomask manufacturer to choose electron beam resists of lower sensitivity. When the resist is exposed by too many electrons, it is excessively heated up to have higher sensitivity at a higher temperature, which results in degraded CD uniformity. This effect is called “resist heating effect” and is now the most critical error source in CD control on a variable shaped beam (VSB) mask writer. We have developed an on-tool, real-time correction system for the resist heating effect. The system is composed of correction software based on a simple thermal diffusion model and computational hardware equipped with more than 100 graphical processing unit chips. We have demonstrated that the designed correction accuracy was obtained and the runtime of correction was sufficiently shorter than the writing time. The system is ready to be deployed for our VSB mask writers to retain the writing time as short as possible for lower sensitivity resists by removing the need for increased pass count.

For robust standard cell design, designers need to improve the intercell compatibility for all combinations of cells and cell placements. Multiple patterning lithography colorability check breaks the locality of traditional rule check, and N-wise checks are strongly needed to verify the colorability for layout interactions across cell boundaries. A systematic framework is proposed to evaluate the library-level robustness over multiple patterning lithography from two perspectives, including complete checks on two-row combinations of cells and long-range interactions. With complete checks on two-row combinations of cells, the vertical and horizontal boundary checks are explored to predict illegal cell combinations. For long-range interactions, random benchmarks are generated by cell shifting and tested to evaluate the placement-level efforts needed to reduce the manufacturing complexity from quadruple patterning lithography to triple patterning lithography for the middle-of-line (MOL) layers. Our framework is tested on the MOL layers but can be easily adapted to other critical layers with multiple patterning lithography constraints.

We try to find out the details of how light fields behind the structures of photomasks develop in order to determine the best conditions and designs for proximity printing. The parameters that we use approach real situations like structure printing at proximity gaps of 20 to 50  μm and structure sizes down to 2  μm. This is the first time that an experimental analysis of light propagation through a mask is presented in detail, which includes information on intensity and phase. We use high-resolution interference microscopy (HRIM) for the measurement. HRIM is a Mach–Zehnder interferometer, which is capable of recording three-dimensional distributions of intensity and phase with diffraction-limited resolution. Our characterization technique allows plotting the evolution of the desired light field, usually called the aerial image, and therefore gives access to the printable structure until the desired proximity gap. Here, we discuss in detail the evolution of intensity and phase fields of elbow or corner structures at different positions behind a phase mask and interpret the main parameters. Of particular interest are tolerances against proximity gap variation and the theoretical explanation of the resolution in printed structures.

The physical process of mask manufacturing produces absorber geometry with significant deviations from the 90-deg corners, which are typically assumed in the mask design. The non-Manhattan mask geometry is an essential contributor to the aerial image and resulting patterning performance through focus. Current state-of-the-art models for corner rounding employ “chopping” a 90-deg mask corner, replacing the corner with a small 45-deg edge. A methodology is presented to approximate the impact of three-dimensional (3-D) EMF effects introduced by corners with rounded edges. The approach is integrated into a full-chip 3-D mask simulation methodology based on the domain decomposition method with edge to edge crosstalk correction.

The mask plays a significant role as an active optical element in lithography, for both deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography. Mask-induced and feature-dependent shifts of the best-focus position and other aberration-like effects were reported both for DUV immersion and for EUV lithography. We employ rigorous computation of light diffraction from lithographic masks in combination with aerial image simulation to study the root causes of these effects and their dependencies from mask and optical system parameters. Special emphasis is put on the comparison of transmission masks for DUV lithography and reflective masks for EUV lithography, respectively. Several strategies to compensate the mask-induced phase effects are discussed.

In optical lithography, high-performance exposure tools are indispensable to obtain not only fine patterns but also preciseness in pattern width. Since an accurate theoretical method is necessary to predict these values, some pioneer and valuable studies have been proposed. However, there might be some ambiguity or lack of consensus regarding the treatment of diffraction by object, incoming inclination factor onto image plane in scalar imaging theory, and paradoxical phenomenon of the inclined entrance plane wave onto image in vector imaging theory. We have reconsidered imaging theory in detail and also phenomenologically resolved the paradox. By comparing theoretical aerial image intensity with experimental pattern width for one-dimensional pattern, we have validated our theoretical consideration.

LELECUT type triple patterning lithography is one of the most promising techniques in 14 nm logic node and beyond. To prevent yield loss caused by overlay error, LELECUT mask assignment, which is tolerant to overlay error, is desired. We propose a method that obtains a LELECUT assignment that is tolerant to overlay error. The proposed method uses positive semidefinite relaxation and randomized rounding technique. In our method, the cost function that takes the length of boundary of features determined by the cut mask into account is introduced.

As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements.

As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.

Achieving satisfactory overlay is increasingly challenging as feature sizes are reduced and allowable overlay budgets shrink to several nanometers and below. Overlay errors induced by wafer processing, such as film deposition and etching, constitute a meaningful fraction of overlay budgets. Wafer geometry measurements provide the opportunity to quantify stress-induced distortions at the wafer level and provide information that can be used in a feedback mode to alter wafer processing or in a feed-forward mode to set wafer-specific corrections in the lithography tool. In order for such feed-forward schemes based on wafer geometry to be realized, there is a need for mechanics models that relate in-plane distortion of a chucked wafer to the out-of-plane distortion of a wafer in a free state. Here, a simple analytical model is presented that shows the stress-induced component of overlay is correlated to a corrected local wafer slope metric for a wide range of cases. The analytical model is validated via finite element (FE) simulations of wafers with nonuniform stress distributions. Furthermore, FE modeling is used here to examine the effect of the spatial wavelength of stress variation on the connection between slope and the wafer stress-induced component of overlay.

Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target for a single design layer. Strictly speaking, this quantity is not directly measurable in the fab. What is of vital importance is the relative edge placement errors between different design layers, and in the era of multipatterning, the different constituent mask sublayers for a single design layer. The critical dimensions (CD) and overlay between two layers can be measured in the fab, and there has always been a strong emphasis on control of overlay between design layers. The progress in this realm has been remarkable, accelerated in part at least by the proliferation of multipatterning, which reduces the available overlay budget by introducing a coupling of overlay and CD errors for the target layer. Computational lithography makes possible the full-chip assessment of two-layer edge to edge distances and two-layer contact overlap area. We will investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour-to-contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic CD-overlay process window (PW) for edge placement errors. For double patterning, the interaction of 4-layer CD and overlay errors is very complex, but we illustrate that not only can full-chip verification identify potential two-layer hotspots, the optical proximity correction engine can act to mitigate such hotspots and enlarge the joint CD-overlay PW.

The use of different illumination source shapes and multipatterning processes used to generate sub–40-nm images can create image placement errors level to level, resulting in significant intrafield overlay errors. These errors arise because of the impact of the different pupil shapes on lens aberrations resolving into image placement errors as well as because different tools will react differently to the same pupil shapes. We compare the impact of two extreme illumination sources on intrafield image placement and its effect on overall pattern overlay. We also discuss a method to empirically isolate and measure the amount of intrafield overlay distortion relative to a reference illumination source and then use the results to correct the resultant image placement errors.

Directed self-assembly (DSA) of block copolymers has shown interesting results for contact hole application, as a vertical interconnection access for CMOS sub-10 nm technology. The control of critical dimension uniformity (CDU), defectivity, and placement error (PE) is challenging and depends on multiple processes and material parameters. This paper reports the work done using the 300-mm pilot line available in materials to integrate the DSA process on contact and via level patterning. In the first part, a reliable methodology for PE measurement is defined. By tuning intrinsic edge detection parameters on standard reference images, the working window is determined. The methodology is then implemented to analyze the experimental data. The impact of the planarization process on PE and the importance of PE as a complement of CDU and hole open yield for process window determination are discussed.

We will summarize our work on mask topography-induced effects over the last 5 years. We will give a full physical explanation of the effects that can be observed from exposed wafers in state-of-the-art immersion and extreme ultraviolet photolithography. The mask topography-induced phase leads to vertical and lateral displacements of the aerial image, resulting in feature-dependent best focus and position. The feature dependency has been studied for gratings through pitch and size and for two-trench arrangements. The physical explanation involves the analysis and quantification of phase effects in a similar way as was done for projection lens aberrations one decade ago. Phase effects, derived both from rigorous simulations and an analytical model, will be compared with exposure figure or merits (e.g., best focus per feature) and correlate well. Therefore, the analysis of mask topography induced phase and the reduction thereof by absorber thickness optimization can be used to drive lithography improvements.

Charging-induced pattern positioning errors (CIPPEs) from a 50-kV variable-shape e-beam writer on an opaque-MoSi-over-glass mask has been carefully characterized by directly measuring the pattern shifts using a high-accuracy mask registration tool. In addition, the reported behaviors associated with the CIPPEs, exponentially decaying in space and sign flipping with increasing pattern density (PD), another seldom-mentioned error component, behaving like a constant offset in space and becoming stronger with increasing PD, is found. The authors repeat the experiment with a charge dissipation layer coated atop the resist to experimentally explore the origins of these two phenomena and find that the exponential components, removable by the charge dissipating layer (CDL), result from the well-known resist charging effect but the constant offset, remain existing with the CDL, does not. From the result of Monte Carlo simulations, the constant component is speculated to result from blank charging. This finding can give important insights into the model-based charging effect correction as well as the effectiveness of the CDL.

Requirements for control of mask registration errors and wafer overlay errors become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Registration control, also known as RegC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting mask registration and wafer overlay. Using an ultrashort pulsed laser, microscopic deformation elements, strain centers, which are also known as pixels, are generated deep inside the fused silica mask substrate causing strain. The induced strain moves the mask pattern in predicted calculated directions to reduce the measured image placement error (IPE). RegC corrections can be applied in two different ways: as a periphery-mask correction, which places the strain centers in the mask frame area outside the exposure field, or as a full-mask correction, that places the strain centers across the entire mask, including the exposure field. Relative pattern displacements up to 1 nm can be achieved between sites located at a distance of 1 mm, reducing the magnitude of the residual IPE by an average of 20% (10% to 25% range) for a periphery correction or 40% (20% to 50% range) for a full-mask correction. The input data for the RegC process are typically taken from mask registration information, which is measured by registration metrology tools or measured from wafer overlay (the latter is not within the scope of this paper). This paper reviews the RegC process flow for improving mask registration in mask shops.

Reticles can be damaged by electric field as well as by the conductive transfer of charge. As device feature sizes have moved from the micro- into the nano-regime, reticle sensitivity to electric field has been increasing owing to the physics of field induction. Hence, the predominant risk to production reticles today is from exposure to electric field. Measurements of electric field that illustrate the extreme risk faced by today’s production reticles are presented. It is shown that some of the standard methods used for prevention of electrostatic discharge in semiconductor manufacturing, being based on controlling static charge and voltage, do not offer reticles adequate protection against electric field. In some cases, they actually increase the risk of reticle damage. Methodology developed specifically to protect reticles against electric field is required, which is described in SEMI Standard E163. Measurements are also presented showing that static dissipative plastic is not an ideal material to use for the construction of reticle pods as it both generates and transmits transient electric field. An appropriate combination of insulating material and metallic shielding is shown to provide the best electrostatic protection for reticles, with fail-safe protection only being possible if the reticle is fully shielded within a metal Faraday cage.

Defect-free fabrication of extreme ultraviolet (EUV) masks relies on the appropriate detection of native defects and subsequent strategies for their elimination. Commercial unavailability of actinic mask-blank inspection systems motivates the identification of an optical inspection methodology most suitable for finding relevant EUV blank defects. Studies showed that 193-nm wavelength inspection found the greatest number of printable defects as compared with rival higher-wavelength systems, establishing deep ultraviolet inspections as the blank defectivity baseline for subsequent mitigation strategies. Next, defect avoidance via pattern shifting was explored using representative 7-nm node metal/contact layer designs and 193-nm mask-blank inspection results. It was found that a significant percentage of native defects could be avoided only when the design was limited to active patterns (i.e., layouts without dummy fill). Total pattern-defect overlap remained ≤5 when metal layer blanks were chosen from the top 35% least defective substrates, while the majority of blanks remained suitable for contacts layers due to a lower active pattern density. Finally, nanomachining was used to address remaining native/multilayer defects. Native catastrophic defects were shown to recover 40% to 70% of target critical dimension after nanomachining, demonstrating the enormous potential for compensating multilayer defects.

The absorber stack on the conventional mask in extreme ultraviolet (EUV) lithography technology leads to mask three-dimensional (3-D) effects including horizontal–vertical (H–V) bias and position shifts through focus. To overcome these problems, we revisit the etched multilayer mask structure. We focus on the etched multilayer mask structure process down to a 16-nm half-pitch at a 0.33 numerical aperture, and we compare the results from this mask to those obtained with a conventional mask. Removing the absorber stack makes the H–V bias of an etched multilayer mask smaller than that of a conventional absorber mask for a 16-nm half-pitch. Thus, the etched multilayer mask can be used to reduce the mask 3-D effects.

Subwavelength gratings exhibit attractive polarizing properties and have promising applications in communication, optical information processing, holography, and displays. The fabrication of subwavelength binary gratings for operation as polarizing beam splitters (PBS) at a wavelength of 1550 nm is presented. A simplified modal method was used for the design as well as to predict the efficiencies of the polarization components in each order. Electron beam lithography has been employed for patterning subwavelength grating structures on polymethyl methacrylate (PMMA) resist. The fixed beam moving stage patterning mode is used for patterning gratings with a period of 936 nm and width of 374 nm. The exposure and developing parameters are optimized to realize the grating with the designed feature sizes on PMMA resist. Gratings patterned using the optimized exposure and development parameters match well with the design, except for the height. The performance of the fabricated PBS grating has been evaluated by optical testing. The experimental results match well with the predictions.

State-of-the-art directed self-assembly (DSA) of block copolymer (BCP) methods still yield defect densities orders of magnitude higher than is necessary in semiconductor fabrication. The defect free energy of a dislocation pair or jog defect, one of the most common defects found in BCP-DSA, is calculated via thermodynamic integration using a coarse-grained molecular dynamics model as a function of χ and the degree of polymerization (N). It is found that χN is not the best predictor of defect free energy and that a single χN value can yield vastly different free energies when χ and N are different. Defect free energy was highly dependent on defect location relative to the underlayer, and free energy differences ∼100  kT were found among the three possible defect locations on a 1:3 guiding pattern. It was found that increasing molar mass dispersity (Ð) significantly reduced defect free energy. Extrapolating from Ð up to 1.5 suggests that the defect will occur in equal proportions to the defect free state at a Ð of around 1.6 for this system. It was found that long chains tended to concentrate near the defect and stabilize the defect.

The absorption of extreme ultraviolet (EUV) light by the mask-protecting pellicle could be the most critical problem preventing widespread EUV adoption because EUV source power is still too limited to facilitate its use in mass production. We found that transmission loss due to the EUV pellicle could be compensated through the use of proper optical proximity correction (OPC) applied to the mask-pellicle system. Patterning results of optical proximity correction corrected masks with different transmission pellicles are shown for various one-dimensional and two-dimensional patterns. From the results, it is clearly shown that we do not need to increase the dose to avoid the throughput loss, even when using a pellicle with 80% one-pass transmission. The OPC process described in this paper can speed EUV adoption by allowing the use of much thicker films with higher absorption.

Extreme ultraviolet lithography (EUVL) patterned mask defect detection is a major issue that must be addressed to realize EUVL-based device fabrication. We have designed projection electron microscope (PEM) optics for integration into a mask inspection system, and the resulting PEM system performs well in half-pitch (hp) 16-nm-node EUVL patterned mask inspection applications. A learning system has been used in this PEM patterned mask inspection tool. The PEM identifies defects using the “defectivity” parameter that is derived from the acquired image characteristics. The learning system has been developed to reduce the labor and the costs associated with adjustment of the PEM’s detection capabilities to cope with newly defined mask defects. The concepts behind this learning system and the parameter optimization flow are presented here. The learning system for the PEM is based on a library of registered defects. The learning system then optimizes the detection capability by reconciling previously registered defects with newly registered defects. Functional verification of the learning system is also described, and the system’s detection capability is demonstrated by applying it to the inspection of hp 11-nm EUV masks. We can thus provide a user-friendly mask inspection system with reduced cost of ownership.

An approach to image-based EUV aberration metrology using binary mask targets and iterative model-based solutions to extract both the amplitude and phase components of the aberrated pupil function is presented. The approach is enabled through previously developed modeling, fitting, and extraction algorithms. We seek to examine the behavior of pupil amplitude variation in real-optical systems. Optimized target images were captured under several conditions to fit the resulting pupil responses. Both the amplitude and phase components of the pupil function were extracted from a zone-plate-based EUV mask microscope. The pupil amplitude variation was expanded in three different bases: Zernike polynomials, Legendre polynomials, and Hermite polynomials. It was found that the Zernike polynomials describe pupil amplitude variation most effectively of the three.

This paper presents a thick-film microelectromechanical systems thermoelectric sensor fabricated by a low-temperature thermally assisted lift-off process. During the process, thick metal or semiconductor films experience controlled breakup due to thermal reflow of the underlying lithographically defined photoresist patterns, thereby facilitating the sacrificial removal of the photoresist. This enables rapid and reliable patterning of thick films that can otherwise be difficult to achieve by conventional processes. Experimental results with a sensor consisting of a 60-junction thick-film antimony–bismuth thermopile demonstrate an electric conductivity of 5.44×106  S/m and a Seebeck coefficient of 114  μV/K per junction, which are comparable to those obtained from bulk materials. Thus, the thick-film sensor can potentially allow low-noise, high-efficiency thermoelectric measurements.

The use of fluorescence in microfluidic optical biodetection requires materials with low-background fluorescence to avoid influencing the desired optical signal with spurious light emission. For the same reason, spurious light emission from galvanoluminescence (GL) should be avoided when fluorescence is used in dielectrophoresis (DEP)-based biosensors. Use of non-noble metal electrodes such as indium tin oxide (ITO) in DEP devices is therefore a concern. We evaluate GL in the context of conditions typical of DEP devices. We experimentally show that use of ITO can result in GL. We also show that GL can be avoided, even with metals that demonstrate strong GL such as Al, by proper selection of operating frequency, which can be determined by measuring the impedance spectrum of the DEP device. In addition, we demonstrate that GL results in broadband emission for all of the salt solutions tested. Broadband emission implies that at least some of the light will pass through typical fluorescence filters if a device exhibits GL. We also show that Ni and Cr electrodes do not exhibit GL and may therefore be suitable as low-cost DEP electrodes.