30 June 2016 Special Section Guest Editorial:Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension
Author Affiliations +
J. of Micro/Nanolithography, MEMS, and MOEMS, 15(2), 021401 (2016). doi:10.1117/1.JMM.15.2.021401
This PDF file contains the editorial “Special Section Guest Editorial:Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension” for JM3 Vol. 15 Issue 02
Starikov: Special Section Guest Editorial: Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension

The second of two planned special sections on Control of IC Patterning Variance has been completed. Here are my impressions of this technology field and of some of the papers featured.

Control of device patterns’ widths, separations, extensions, and overlaps1,2 may be broken into two parts: one dealing with variations in one-layer design rules (DRs) and the other in two-layer DRs. These are the topics covered in Part 1 (Metrology, Process Monitoring, and Control of Critical Dimension, which appeared in JM3 Vol. 14, Issue 2) and Part 2 (Image Placement, Device Overlay and Critical Dimension, in this current issue), respectively. Together, they cover almost every aspect of device pattern variation. But, as this guest editor discovered firsthand, a special section “is like a box of chocolates... .”

The field of CD-related metrology for process control, squarely within the scope of Part 1, went through big changes, from CD-SEM–based measurement of critical dimension (CD) to optical scatterometry–based metrology of CD, height, and sidewall angle. The long anticipated applications for direct estimation, monitoring, and control of key process parameters, such as on-wafer monitors of effective exposure dose and focus in lithography, have emerged and enabled tighter control of lithography processes and of patterned device dimensions required for extending optical microlithography. What used to be “off roadmap metrology” is now a part of ITRS, yet only a few glimpses of this can be found in Part 1: Metrology, Process Monitoring and Control of Critical Dimension. Perhaps, it is because the main “movers and shakers” in this field have moved on to other fields or out of the industry. Perhaps, with arguments for direct metrology and control of dose and focus for better CD control settled—despite the issues with tool matching, in situ versus standalone, metrology on generic versus dedicated monitor structures, and the lack of standard methods and calibration—this became a routine and often proprietary matter.

However, Part 1 contains discussions of e-beam based metrology and inspection for OPC design and one-layer DR validation—an area where the industry lacks the essential capability to ascertain DR compliance in-line, preferably well before the end-of-line testing. Technical analysis3 of metrology of edge placement error4 (EPE) reads like a thriller. It also shows that, even with pattern placement as a floating variable and despite using the same tool and edge detection algorithm, a mere comparison of conventional CD-based versus contour-based metrology is not an easy task. Our industry will, likely, keep demanding such capabilities and debating their accuracy for some time yet.

Dealing with two-layer DRs on real wafers is much more difficult. For example, edge-to-edge overlay5 (EE OL) in two layers’ patterns’ separation and extension (also known by application-specific terms “poly-to-active endcap,” “contact-to-metal enclosure,” “contact-to-metal space,” etc.) involves critical dimensions in both patterns and their centerline layer-to-layer overlay. Capability of direct in-line EE OL metrology still does not exist—another gap in DR validation. Although EE OL may be estimated using in-line measurements of two layers’ CDs and OL, in IC manufacturing practice,6 the required CDs and OL are not measured on the same tools or on the same patterns, and their respective control loops are separate. However, two-layer DRs being yield-limiting parameters and OL their largest component, EE OL recently got much attention, with EPE declared as the overlay-related lithography technology showstopper… What does EPE, the foundation of model-based OPC, have to do with overlay? Nothing: this EPE is not that EPE. Although the recent appearance of the term EPE in the industry’s dialog on EE OL may appear as a sign of discovery, no new control parameter was identified. It is still the old one, just a new name. The new language denies the very existence of two-layer DRs and ignores the long-present gaps in DR validation and control. Not only is the new language not helpful in closing the technology gaps, the resulting confusion disrupts the industry dialog on the real issues. Be that as it may, confusing language is not an obstacle for you to comprehend Part 2: Image Placement, Device Overlay, and Critical Dimension. Our authors made an effort to “speak standard SEMI” and to use standard JM3 acronyms whenever possible, and to define or at least illustrate exactly what they mean by the terms which others may find confusing. In one case, you are given the motivation for a new definition, terminology, and performance metric in a new application. Authors rigorously define the subject, explain why those changes are needed, and even trace their new definition to the long-existing SEMI standard. Would you, JM3 reader, expect anything less?

Control of IC Patterning Variance Part 2: Image Placement, Device Overlay, and Critical Dimension does not have papers on the usual “flavors” of metrology of image placement such as alignment, registration, and overlay. However, there are abundant accounts of metrology of image placement by metrology users, very interesting in their own right: registration metrology on photomasks, modeled and experimental CD-SEM based metrologies of device and alignment/metrology targets’ overlay, even of pattern placement in directed self-assembly. There is also the latest learning of pattern placement variation and of its control: wafer stress-induced component of overlay, charging-induced pattern placement error in photomasks, feature- and tool-specific placement errors in lithography for both device and OL measurement structures, etc.

Part 2 represents a significant advancement in our collective understanding of the sources of IC pattern variation affecting the two-layer design rules, and of the new approaches to their control. Whether you are interested in industry, technology, or competitive learning, Part 2 does not disappoint. Within its broad scope, it contains something for almost every interest and taste. I hope that you will enjoy it, too.


1. C. A. Mead and L. A. Conway, “Introduction to VLSI systems, 1978 Prepublication drafts,” March 20, 2008 < http://ai.eecs.umich.edu/people/conway/VLSI/VLSIText/VLSIText.html> (21 June 2016). Google Scholar

2. L. Conway, “Reminiscences of the VLSI revolution: how a series of failures triggered a paradigm shift in digital design,” IEEE Solid State Circuits Mag. 4(4), 8–31 (2012). http://dx.doi.org/10.1109/MSSC.2012.2215752 Google Scholar

3. F. Weisbuch and K. Jantzen, “Enabling scanning electron microscope contour-based optical proximity correction models,” J. Micro/Nanolith. MEMS MOEMS 14(2), 021105 (2015). http://dx.doi.org/10.1117/1.JMM.14.2.021105 Google Scholar

4. N. B. Cobb, “Fast optical and process proximity correction algorithms for integrated circuit manufacturing,” PhD Thesis, Univ. of California at Berkeley (1998). Google Scholar

5. Jr. R. M. Booth et al., “A statistical approach to quality control of non-normal lithographical overlay distributions,” IBM J. Res. Dev. 36(5), 835–844 (1992).IBMJAEIBMJAE0018-8646 http://dx.doi.org/10.1147/rd.365.0835 Google Scholar

6. A. Starikov, “Metrology of image placement,” Chapter 17 in Handbook of Silicon Semiconductor Metrology, and A. C. Diebold, Ed., Marcel Dekker, Inc., New York (2001). Google Scholar

© 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)
Alexander Starikov, "Special Section Guest Editorial:Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension," Journal of Micro/Nanolithography, MEMS, and MOEMS 15(2), 021401 (30 June 2016). https://doi.org/10.1117/1.JMM.15.2.021401


Back to Top