Threshold voltage variability induced by spacer- and resist-defined patterning techniques in nanoscale FinFETs

Rituraj Singh Rathore; Rajneesh Sharma; Ashwani K. Rana

doi:10.1117/1.JMM.16.1.013503

16 February 2017 Threshold voltage variability induced by spacer- and resist-defined patterning techniques in nanoscale FinFETs

Rituraj Singh Rathore, Rajneesh Sharma, Ashwani K. Rana

Author Affiliations +

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 16, Issue 1, 013503 (February 2017). https://doi.org/10.1117/1.JMM.16.1.013503

Abstract

In aggressively scaled devices, FinFET technology has become more prone to line-edge roughness (LER) induced threshold voltage variability. To explain this challenge, all possible LER-induced fin shape variabilities in spacer-defined patterning (i.e., correlated LER) and resist-defined patterning (i.e., uncorrelated LER) technology have been investigated for 14-nm underlap FinFET using 3-D numerical simulations. All LER-induced VTH variabilities are analyzed in the presence of other intrinsic variability sources, such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV). This study reveals that the percentage threshold voltage (VTH) fluctuations of combined effects (RDF, WFV, and OTV) in spacer-defined and resist-defined FinFETs with respect to rectangular FinFET are 2.88% and 8.76%, respectively.

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Rituraj Singh Rathore, Rajneesh Sharma, and Ashwani K. Rana "Threshold voltage variability induced by spacer- and resist-defined patterning techniques in nanoscale FinFETs," Journal of Micro/Nanolithography, MEMS, and MOEMS 16(1), 013503 (16 February 2017). https://doi.org/10.1117/1.JMM.16.1.013503

Received: 22 October 2016; Accepted: 1 February 2017; Published: 16 February 2017

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