This PDF file contains the editorial “2016 List of Reviewers” for JM3 Vol. 16 Issue 01

Measurement of line-edge or linewidth roughness involves uncertainty, like all measurements, and an estimate of that uncertainty should be reported whenever a roughness measurement is reported. However, roughness measurement uncertainty estimates are complicated by the correlations along the length of the rough feature. As a result, roughness measurements are often not accompanied by uncertainty estimates or error bars on graphs. Here, both theoretical considerations and simulations of random rough features will be used to derive a simple formula to estimate the uncertainty of a roughness measurement using the standard parameters describing that roughness: standard deviation, correlation length, and roughness exponent. Additionally, a more accurate formula to estimate the systematic bias in roughness standard deviation is provided.

X-ray differential phase-contrast imaging (DPCI) using a Talbot–Lau interferometer at a conventional tube source has continuously found applications since its first demonstration. It requires high aspect ratio grating structures with a feature size in the micrometer range that are fabricated using lithographie, galvanik und abformung technology. To overcome the current limitation in grating area, an exposure strategy—continuous exposure—has been developed. In this case, the mask is fixed in respect to the synchrotron beam and only the substrate is scanned. Thus, the grating area is given by the scanning length which is much larger than the actual mask size. The design, needs, and tolerances to adopt this process of dynamic exposure will be described. Furthermore, the first tests using this method will be presented. Gratings with a metal aspect ratio of 11 and a period of 10  μm were fabricated on an area of 165  mm×65  mm. First imaging results demonstrate the suitability of this method. No differences in the visibility or in x-ray image compared to gratings fabricated by the standard method could be found.

We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.

In aggressively scaled devices, FinFET technology has become more prone to line-edge roughness (LER) induced threshold voltage variability. To explain this challenge, all possible LER-induced fin shape variabilities in spacer-defined patterning (i.e., correlated LER) and resist-defined patterning (i.e., uncorrelated LER) technology have been investigated for 14-nm underlap FinFET using 3-D numerical simulations. All LER-induced VTH variabilities are analyzed in the presence of other intrinsic variability sources, such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV). This study reveals that the percentage threshold voltage (VTH) fluctuations of combined effects (RDF, WFV, and OTV) in spacer-defined and resist-defined FinFETs with respect to rectangular FinFET are 2.88% and 8.76%, respectively.

We discuss the impact of various noise sources and the optical design in bright field extreme ultraviolet (EUV) actinic inspection of mask features for defects in the patterned absorber. It is shown that an optimum pixel size is needed to maximize the defect signal-to-noise ratio (SNR) to balance the trade-off in increasing signal strength with shot noise from defect signal and the background pattern intensity (mask layout image) and speckle noise from the mask blank roughness. Moreover, we consider defocus showing that the EUV mask phase effect has an asymmetric impact on pattern defect SNR’s through-focus behavior. The impact of defocus limits inspection performance based on defect SNR. Using critical defect sizes in a case study, we show the defect SNR performance of the limiting case and discuss the possibility of utilizing a nominal defocus in the inspection system to leverage the phase effect of EUV mask absorber to improve the defect SNR. A 50% improvement in defect SNR is shown to be possible by introducing a −50  nm nominal defocus into the bright field inspection system.

Directed self assembly (DSA) is a very promising patterning technology for the sub-7-nm technology nodes, especially for via/contact layers. In the graphoepitaxy type of DSA, a complementary lithography technique is used to print the guiding templates, where the block copolymer (BCP) phase-separates into regular structures. Accordingly, the design-friendliness of a DSA-based technology is affected by several factors: the complementary lithography technique, the legal guiding templates, the number of masks/exposures used to print the templates, the related design rules, the forbidden patterns (hotspots), and the characteristics of the BCP. Thus, foundries have a huge number of choices to make for a future DSA-based technology, affecting the design-friendliness, and the cost of the technology. We propose a framework for DSA technology path-finding, for via layers, to be used by the foundry as part of design and technology co-optimization. The framework optimally evaluates a DSA-based technology in which an arbitrary lithography technique is used to print the guiding templates, possibly using many masks/exposures, and provides a design-friendliness metric. In addition, if the evaluated technology is not design-friendly, the framework computes the minimum-cost technology change that makes the technology design-friendly. The framework is used to evaluate technologies like DSA+193-nm immersion (193i) lithography, DSA+extreme ultraviolet (EUV), and DSA+193i self-aligned double patterning. For example, one study showed that one mask of EUV in a DSA+EUV technology can replace three masks of 193i in a DSA+193i technology.

Semiconductor devices continue to shrink in size with every generation. These ever smaller structures are challenging the resolution limits of current analytical and inline metrology tools. We will discuss the results of a study of critical dimension small angle x-ray scattering (CDSAXS) comparing the measured intensity from a laboratory source and a synchrotron to determine the improvements in compact x-ray source technology necessary to make CDSAXS a high throughput metrology method. We investigated finFET test structures with and without a high-k gate dielectric coating. The HfO2-based high-k gate dielectric substantially increased the scattering intensity. We found that single-angle laboratory source measurements of 15 min from HfO2-coated finFETs had sufficient scattering intensity to measure the higher order peaks necessary for obtaining high-resolution dimensional fits. Identical bare silicon finFETs required at least 2 h of exposure time for equivalent data quality. Using these structures, we measured the scattering efficiency and determined the required photon flux for next generation x-ray sources to make an inline CDSAXS tool high throughput.

This paper aims to fabricate high aspect ratio through silicon via (TSV) by photo-assisted electrochemical etching (PAECE) and supercritical CO2 copper electroplating. A blind-holed silicon array was first fabricated by PAECE. By studying the etching parameters, including hydrofluoric acid concentration, etchant temperature, stirring speed, tetrabutylammonium perchlorate (TBAP) content, and Ohmic contact thickness, an array of pores with a 1∶45 aspect ratio (height=250  μm and diameter=5.5  μm) was obtained successfully. Moreover, TBAP and Kodak Photo-Flo (PF) solution were added into the etchant to acquire smooth sidewalls for the first time. TBAP was added for the first time to serve as an antistatic agent in deionized water-based etchant to prevent side-branch etching, and PF was used to degasify hydrogen bubbles in the etchant. The effect of gold thickness over Ohmic contact was investigated. Randomized etching was observed with an Au thickness of 200 Å, but it can be improved by increasing the etching voltage. The silicon mold of through-holes was filled with metal using supercritical CO2 copper electroplating, which features high diffusivity, permeability, and density. The TSV structure (aspect ratio=1∶35) was obtained at a supercritical pressure of 2000 psi, temperature of 50°C, and current density of 30  mA/cm2 in 2.5 h.

We report the critical factors that control the geometry of silicon nanostructures produced by metal-assisted chemical etching (MacEtch) using self-assembled islands from an ultrathin film of gold. We have conducted a systematic study of the process parameters that control the geometry of the metal structures and the resulting etched nanostructures. Compared to prior reports, which have focused on the crystal orientation and solution stoichiometry, our study finds that the anisotropy of the etched nanostructures is primarily controlled by the deposited metal geometry, while solution stoichiometry and crystal orientation play relatively minor roles. Using an optimized self-assembled geometry and etch process, we demonstrate what we believe is the highest aspect ratio to date (greater than 5000∶1) for high density top-down etched silicon nanostructures. These structures, which we refer to as silicon nanowalls, are in the size regime where quantum confinement effects could potentially be exploited for next-generation optoelectronic components and devices.

The traversal rate for the liquid medium near a point-of-care testing (POCT) device microfluidic channel edge is faster than that through the body of the channel, which makes the fluid front meniscus becomes concave rather than convex or flat. The concave front is unwished due to its influences on quantitative analysis accuracy and the possibility to generate air bubbles. Here, a unique method, named hydrophobic marking line, is demonstrated. This method used a soft pen with hydrophobic ink to draw two lines along the edges of the channel of a POCT device. Results have shown that the marking lines will eliminate the edge effects and generate convex liquid front. The curvature of the liquid front can be changed by adjusting the marking line width or ink solutions.

A gas sensor based on microelectromechanical systems (MEMS) technology containing a WO3 sensitive layer was designed, simulated, and fabricated. The gas sensor consists of a silicon substrate, a platinum microheater, gold interdigitated electrodes, and a WO3 sensitive layer. The active area with dimensions of 0.4  mm×0.4  mm is located at the center of a sensor (3  mm×3  mm). The experimental results show that the microheater provided heating for the WO3 sensitive layer at low power consumption and accurate temperature control. At a power consumption of only 40 mW, the temperature reached 319°C at the center of the MEMS platform with uniform heating. In addition to that, the above mentioned gas sensor exhibited a high response to NO2 with optimized sensitivity recorded at the working temperature of 170°C. With 10 ppb of NO2, the response of the sensor could reach up to 5.8 and the power consumption is 17.2 mW.

This paper reports the theoretical study and estimations of thermal mismatch stress reduction in anodically bonded silicon–glass stacks by justifiable selection of bonding temperature and glass thickness. This can be done only after prior thorough study of temperature dependence of the linear thermal expansion coefficient of the glass and silicon to be used. We show by analyzing such a dependence of several glass brands that the usual idea of decreasing the bonding process temperature as a solution to the thermal mismatch stress problem can be a failure. Interchanging glass brands during device design is shown to produce very contrasting changes in residual stresses. These results are in good agreement with finite-element modeling. This paper reports there is proportion between glass and silicon wafer thicknesses minimizing thermal mismatch stress at unbonded side of the silicon independently of the bonding or working temperatures chosen.

A SOIMUMPs 1-D rotation micromirror is presented. The micromirror is driven by electrostatic vertical comb-drive actuators to work at resonant mode to scan a laser beam. The residual stress in the metal film coated on the SOI device layer is used to generate vertical offset in the comb-drive actuators with the combs located far from the rotation axis to increase the torque. A concave lens is designed to put after the micromirror to amplify the laser beam scanning angle, as well as to compensate for the curvature of the micromirror. A micromirror-based scanning system is used to build a laser line generator with a continuously adjustable fan angle, which solves the limitation of a fixed fan angle in conventional laser line generators. Prototypes of the micromirror and the laser line generator are fabricated and measured. A driving circuit that can generate a high-voltage square wave driving signal with adjustable amplitude and frequency is designed. All the parts are integrated in a 44  mm×88  mm×44  mm box and powered with a single 5-V power supply. The optical scanning angle under 100 V with or without the concave lens is 27 deg and 12 deg, respectively, at a resonant frequency of 900 Hz.

This PDF file contains the errata for “JM3 Vol. 16 Issue 01 Paper JM3-2017-0203-ERR” for JM3 Vol. 16 Issue 01