This PDF file contains the editorial “Making double patterning cost single” for JM3 Vol. 8 Issue 01

This PDF file contains the editorial “Guest Editorial: Double-Patterning Lithography” for JM3 Vol. 8 Issue 01

Double patterning lithography (DPL)-either with two litho and two etches or through the use of a sacrificial spacer-are comparable in complexity and process control requirements. Since critical dimensions uniformity (CDU) and overlay requirements are considerably tighter than in single exposure, they present tougher challenges to process control, metrology, and integration, but seem feasible for 32-nm node. We study CDU and overlay requirements and performance at 32-nm-hp resolution for dual litho-etch and sacrificial spacer schemes. We bring in three particular aspects of CD control: the existence of multiple populations of lines and spaces, overlay entanglement into CDU performance, and the mechanism of doubled-pitch pattern generation from uncorrelated left and right edges, Accordingly, active compensation schemes are proposed to bring together these multiple CDU populations in order to achieve the typical 10% CD tolerance of the final pattern. Experimental results confirmed our assumptions of CDU-overlay entanglement and existence of multiple CD populations of lines and spaces. We present CDU results from before and after applying CD compensation schemes to improve CDU and overlay performance through active feed forward corrections. Results confirm the gain in improving statistical and spatial CD distribution to meet control levels required at 32-nm design rules: 2-nm CDU control per population, 3-nm CDU control for two adjacent lines, or spacer CD populations with 3-nm single machine overlay, all of them being demonstrated on multiple wafers and immersion scanners.

Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are being considered. This paper focuses on the requirements of the most complex forms of DP, pitch-splitting (where line density is doubled through two exposures) and spacer processes (where a deposition process is used to achieve the final pattern). Budgets for critical dimension uniformity and overlay are presented along with tool and process requirements to achieve these budgets. Experimental results showing 45-nm lines and spaces using dry ArF lithography with a k₁ factor of 0.20 are presented to highlight some of the challenges. Finally, alternatives to DP are presented.

Double patterning (DPT) lithography is seen industry-wide as an intermediate solution for the 32-nm node if high index immersion as well as extreme ultraviolet lithography are not ready for a timely release for production. Apart from the obvious drawbacks of the additional exposure, the processing steps, and the resulting reduced throughput, DPT possesses a number of additional technical challenges. This relates to, e.g., exposure tool capability, the actual applied process in the wafer fab, but also to mask performance and metrology. In this work we address the mask performance. To characterize the mask performance in an actual DPT process, conventional mask parameters need to be re-evaluated. Furthermore, new parameters might be more suitable to describe mask capability. This refers to, e.g., reticle to reticle overlay, but also to CD differences between masks of a DPT reticle set. For the 32-nm node, a DPT target of reticle to reticle induced overlay of 6 nm, 3σ at mask level, was recently proposed. We report on the performance of a two-reticle set based on a design developed to study the impact of global and local mask placement errors on double patterning using a dual-line process. In a first step we focus on reticle to reticle overlay based on conventional mask metrology. The overlay between two masks evaluated for standard wafer overlay targets is compared with measurements on actual resolution structures, contributions of displacements on different spatial scales are discussed, and mask to mask CD variations are addressed. In a second step, we compare reticle data with experimental intrafield overlay data obtained from wafers on an ASML XT:1700i using the IMEC dual-line double patterning process. Reticle to reticle overlay contribution is studied on the wafers for both standard overlay targets and dedicated DPT features. The results of this study show...

A practical approach, adopting a clever litho trim, to spacer double patterning is investigated in detail. In order to produce quarter-pitch small lines of dense arrays (with pitch fragmentation techniques), state-of-the-art ArF photoresists can be used with a subsequent trim etch, to get the tiny line widths on desired target. Critical dimension (CD) control during the trim etch process plays a crucial role. Therefore, we investigated the application of a litho trim in order to reduce the trim etch close to zero bias. This approach has the further advantage to allow the printing of small spaces together with small lines, which reduces the k₁ and, therefore, the theoretical resolution. Applying CD trim by litho “overexposure,” thin ArF bilayer system (silicon containing resist on spin-on carbon underlayer) showed basic suitability at k₁=0.146 at half pitch of 3xnm with a sufficient process window and a good CD uniformity after litho and after etch. ArF single-layer resists suffer from pattern collapse and resist thickness loss at defocus. For spacer deposition directly on resist, the control of profiles and film thicknesses is shown to be difficult using single-layer resists and more likely to be achieved with bilayer resists. It is also shown that spacer-based double patterning can generate good CD uniformity by use of bilayer resist and litho trim, both with an a-Si carrier and bilayer resist carrier (underlayer).

Double patterning is considered the most viable option for 32- and 22-nm complementary metal-oxide semiconductor (CMOS) node development and has seen a surge of interest due to the remaining challenges of next-generation lithography systems. Most double patterning approaches previously described require intermediate processing steps (e.g., hard mask etching, resist freezing, spacer material deposition, etc.). These additional steps can add significantly to the cost of producing the double pattern. Alternative litho-only double patterning processes are investigated to achieve a composite image without the need for intermediate processing steps. A comparative study between positive–negative (TArF-P6239+N3007) and positive–positive tone (TArF-P6239+PP002) imaging is described. In brief, the positive–positive tone approach is found to be a superior solution due to a variety of considerations.

Double-patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double-patterning process is discussed for 30-nm half-pitch interconnect structures, using 1.2 numerical aperture immersion lithography combined with the Motif^TM critical dimension (CD) shrink technique. An adjusted optical proximity correction (OPC) calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography-based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30-nm half-pitch pattern into the MHM.

The extension of optical lithography to 32 nm and beyond is dependent on double-patterning at critical levels. Double patterning adds degrees of freedom for overlay variation while reducing the allowed overlay tolerance. Overlay control requires the assessment and minimization of error among various mask/layer combinations. The possible overlay control combinations scale as C_n=(2ⁿ−1)² with the number of reference layers n containing (x,y) alignment and overlay targets. Finding the optimum overlay control pathway requires that we employ the on-product means to examine multiple options compatible with the product overlay tolerances. The Blossom overlay target enables simultaneous determination of all combinations of patterns represented within the measurement tool field of view. We examine Blossom enabled use cases in double patterning overlay control as demonstrated at contact-to-gate registration on a 32 nm product.

Variation in the critical dimension (CD) of a transistor is a primary concern for advanced lithography. Because variation from sources such as corner rounding or line edge roughness does not scale with CD, variability in transistor performance increases with scaling and may impact the timing or even the functionality of critical circuits such as static random access memories (SRAM) and ring oscillators. Spacer lithography is an attractive patterning method for future technology nodes, because its use of a very uniform and controllable chemical vapor deposition (CVD) step allows for the definition of very narrow lines with low variation and reduced pitch. In practice, however, the possible pitch reductions are limited by the need for conventional lithography to produce negative features (e.g., trenches and holes) and increasing CD variability with iterated spacer processing. In this work, an extension to spacer lithography is presented to overcome these limitations. Negative features down to 30 nm in width are fabricated using spacer-defined features. A multitiered hard mask process is also presented to enable eight-fold pitch reduction with no increase in CD variation. In combination, these processes enable ultradense circuit integration for regular layouts.

Many processes are under evaluation as simplifications to current double patterning methods. Reduction in process complexity and cost may be achieved by use of track-based photoresist stabilization methods that eliminate one etch step by allowing a second resist to be patterned over a first resist. Examples of stabilization methods using numerous curing processes have been reported. At least some resist shrinkage during stabilization appears to be generally observed for these methods. We evaluate the link between shrinkage and three-dimensional pattern distortions at line ends and elbow corners using experimental and simulation-based methods. A 172-nm UV resist curing process was used to produce controlled shrinkage ranging from 5% to 30%: shrinkage was correlated with resist distortions. At cure dose sufficient to stabilize the resist, shrinkage of approximately 23% results in measured line-end pullback and elbow displacement of approximately 16% and 13% of nominal linewidth respectively, when measured at resist half-height. Finite element analysis of resist beam structures produces shrinkage distortions that are in good qualitative and semiquantitative agreement with these measurements and thus appears to provide a provisionally general and useful method for predicting pattern distortions that arise during cure-based resist stabilization methods used in double imaging.

The current optical photolithography technology is approaching the physical barrier to the minimum achievable feature size. To produce smaller devices, new resolution enhancement technologies must be developed. Double-exposure lithography has shown promise as a potential pathway that is attractive because it is much cheaper than double-patterning lithography and can be deployed on existing imaging tools. However, this technology is not possible without the development of new materials with nonlinear response to exposure dose. The performance of existing materials such as reversible contrast enhancement layers (rCELs), and theoretical materials such as intermediate state two-photon (ISTP) and optical threshold layer (OTL) materials in double-exposure applications have been investigated through computer simulation. All three materials yielded process windows in double-exposure mode. OTL materials showed the largest process window (depth of focus (DOF) 0.14 µm, exposure latitude (EL) 5.1%). ISTP materials had the next-largest process window (DOF 0.12 µm, EL 3.2%), followed by the rCEL (0.11 µm, 0.58%). This study is an analysis of the feasibility of using the materials in double-exposure mode.

For lithography of 45-nm half-pitch and beyond, the resist blur due to photoacid diffusion is a significant issue. On the other hand, it has been generally recognized that there is a trade-off between resist resolution and sensitivity. We study the influence of the resist blur on resolution in hypernumerical aperture ArF immersion lithography by utilizing a two-beam interferometric exposure tool. We evaluated the current photoresist performance for some of the latest commercial resists and estimated their acid diffusion lengths as 8 nm to 9 nm in sigma assuming Gaussian blur kernel. In addition, we found that the acid diffusion length, which is directly related to the resist resolution and is controllable by photoacid generator (PAG) anion size, polymer resin size, and post-exposure bake (PEB) temperature. We confirmed that there is a trade-off between resist resolution and sensitivity. Our results indicate that the resist blur is still a concern in order to extend lithography for 45 nm and beyond; however, it will not likely be a showstopper. We consider that total optimization of resists and exposure tools is important in order to achieve ultimate resolution in hyper-NA immersion lithography.

We make a new model for pattern failure, which is the pattern collapse and bridging of resist patterns of 43-nm 1:1 lines and spaces (L/S) exposed as a focus-exposure matrix, to explain and predict the process window of the pattern failure. It is found that the conventional Imax-Imin model cannot be fitted to the experimental pass/fail data. Instead of Imax and Imin, we select the critical dimension (CD) and normalized image log slope (NILS) as the model input. The new CD-NILS model corresponds well to the experimental pass/fail data. Good correspondence is assumed to be due to the properly selected model input. Pattern collapse, which occurs during the drying of the water at the rinse of the resist patterns, is expected to be accelerated by the smaller line CD and the larger line width roughness (LWR) due to smaller NILS. Pattern bridging, which occurs during resist development, is expected to be accelerated by the larger line CD and the larger LWR. The CD-NILS model predicts the process window precisely when a new process condition (a new illumination in this case) is adopted. It suggests that the CD-NILS model is a powerful methodology for predicting the process window to optimize the process condition and optimize the lithography design.

Spatially varying grating structures formed at the subwavelength scale behave as a layer with an artificial effective refractive index that is dependent on the local fill fraction. We describe a novel technique to pattern gratings with a spatially varying fill fraction using a simple two-step exposure process. The first exposure forms a partial latent image of a grating in the photoresist. The resist is then saturated by overlaying an exposure with an analog spatially varying intensity, generated by using a phase-only masking technique. The cumulative exposure dose from the two steps was designed so that the point of minimum intensity will still develop the photoresist through, in all the spaces in the grating. By varying the exposure window around the saturation dose, the fill fraction of the patterned gratings was modulated; thus, the size of the space cleared at any location in the grating is a scalable function of the local cumulative dose delivered. Constant feature height is achieved across the patterned area by keeping the second exposure dose below the resist threshold exposure value. The exposure process was modeled numerically to predict the relationship between the local dose and patterned fill fraction. This technique enables rapid, low-cost fabrication of apodized grating structures for applications in diffractive optics technology.

The development of both “soft” and “hard” fabrication techniques for the patterning of nonlinear photonic devices in ionically self-assembled monolayer (ISAM) films is reported. A combination of electron beam lithography and reactive ion etching was used to pattern two-dimensional holes with a lattice of 710 nm and diameters ranging from 550 to 650 nm. A soft alternative to this fabrication was also demonstrated. Nanoimprint lithography was successfully employed to pattern similar photonic structures with average hole diameters of 490 nm and a lattice spacing of 750 nm, as well as Bragg gratings with a period of 620 nm. Potential impact of this fabrication process on the chemical composition and nonlinear properties of the ISAM films was assessed using Fourier transform infrared spectroscopy, x-ray photoelectron spectroscopy, and second harmonic generation. The spectroscopy techniques confirmed that the chemical composition and bonding of the ISAM films was not adversely affected by the thermal cycles required for nanoimprinting. Second harmonic generation analysis also confirmed that the nanoimprinting process did not affect the nonlinear properties of the material, PCBS/PAH ISAM films, further indicating the suitability of such materials for the nanoimprinting of nonlinear optical photonic structures.

Modification for substrate surface morphology is a kind of effective technique for controlling thin film growth orientation. In this work, continuous V-grooves are fabricated on monocrystalline Si(100) substrate using TiO₂ resist mask by anisotropic wet etching. Influence of thickness of TiO₂ resist mask on etching patterns is investigated. The integrity and cross section of V-grooves are observed by laser scanning confocal microscope (LSCM) and scanning electronic microscopy (SEM), respectively. The floccules precipitating in V-grooves are verified by an energy dispersive spectrometer (EDS). Results indicate that the Si(100) substrate surface is modified to the array of V-grooves along the Si[010] direction with Si(110) sidewalls.

We report the direct etching of Al₂O₃ and SiO₂ using 900-keV Au⁺ ions. 2000-mesh Cu grids were employed as masks using two different configurations: (1) the Cu mesh was placed on top of each insulator separately and independent irradiations were performed, and (2) the Al₂O₃ and SiO₂ substrates were positioned in an edge-to-edge configuration with a single Cu grid providing a common mask to both insulators. Scanning electron microscopy (SEM) analysis revealed quite different patterns resulting from the two irradiation configurations. While the irradiation using individual masks resulted in mirror-image patterns of the Cu mask in the substrates, the use of a common mask led to single line structures approximately normal to the edges of the substrates. The role of charge buildup and sputtering in relation to relative dielectric properties of the substrates and close proximity of the samples during irradiation is discussed.

For sub-50-nm semiconductor patterning processes, extremely coherent illumination and high-transmission (Hi-T) attenuated background phase-shifting reticles are becoming increasingly important in delivering high-quality aerial images. Here, a Hi-T reticle is defined as any attenuated phase-shifting mask with a background transmission intensity of 12% or higher of incident light. While numerical simulation has served as a powerful tool in reticle design, the analytical relation of image log slope (ILS) and mask error enhancement factor (MEEF) are calculable in concise, exact form to reveal additional insight into reticle optimization. The properties of ILS and MEEF can be derived analytically in predicting the optimal range of mask bias in terms of image contrast and sensitivity for improved critical dimension (CD) control. These derived relations also demonstrate the capability for analysis beyond extensive numerical simulation and can be easily scaled and applied to various pitches and mask CDs. These relations are also verified in this paper with simulation of realistic process parameters and thus prove the applicability in optimization of Hi-T reticles.

We report a fabrication of doubly supported free-standing buckminsterfullerene (C₆₀) nanowires onto single crystal silicon microstructures in order to demonstrate an integration of carbon nanomaterials to surface-micromachined microelectromechanical devices. By irradiating vacuum-deposited C₆₀ film with an electron beam, polymerized C₆₀ nanowires were patterned. Free-standing structures of the C₆₀ nanowires were obtained by sacrificial etching of underlying silicon structures using XeF₂ gas. The supporting 5-µm thick silicon structure was released using vapor hydrofluoric acid. The C₆₀ nanowire of 2-µm width, 25-µm length, and 40-nm thickness connected to a movable single crystal silicon structure was successfully fabricated.

We report the design, fabrication, and measurements of a dual-reflective, single-crystal silicon-based micromirror that can perform circumferential scanning for endoscopic optical coherence tomography (EOCT). Full 360-deg optical scan angle (OSA) can be achieved by using a dual-reflective mirror with ±45-deg (or 90-deg) mechanical scan angle (MSA), where each reflective mirror surface contributes a 180-deg optical scanning. A novel surface- and bulk-combined micromachining process based on silicon on insulator (SOI) wafers is developed for fabricating the dual-reflective micromirror. The mirror flatness is maintained by the single-crystal-silicon device layer of SOI wafers, and aluminum is coated on both sides for reflection. A fabricated device demonstrated about half circumferential scanning range at resonance of 425 Hz. Other measured data include the radii of curvature, −129 mm (front surface) and 132 mm (back surface), and the reflectance, 86.3% (front surface) and 84.2% (back surface). This micromirror has the potential to realize full-circumferential-scanning EOCT imaging.

Fabrication process of through-Si-via (TSV) interconnects and their electrical characterization method were investigated for 3-D stacked packaging. A prototype, three-layer module with a flip-chip bonding process with anisotropic conductive film (ACF) was fabricated with the process. To measure a single interconnect resistance, a Kelvin structure was designed and applied on the chip and substrate. A theoretical model to calculate the connection resistance of the 3-D TSV interconnects was also derived and used to verify the experimentally measured resistance by applying the Kelvin structure designed. Optimum conditions for the formation of through-holes with the deep reactive ion-etching process were a coil power of 200 W, cycle time of 6.5/5 s, and SF₆:C₄F₈ gas flow rate of 260:100 sccm. Pulse-reverse current provided the finest grain growth during the Cu electroplating and thus prevented the trapping of voids. The experimentally measured resistance was successfully verified by the theoretical model, and the model shows that the resistance value was mainly contributed by the ACF interconnect, not by TSVs.