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28 February 2019 All-optical logic gates based on nanoring insulator–metal–insulator plasmonic waveguides at optical communications band
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Abstract
We propose, analyze, and simulate a configuration to realize all-optical logic gates based on nanoring insulator–metal–insulator (IMI) plasmonic waveguides. The proposed plasmonic logic gates are numerically analyzed by finite element method. The analyzed gates are NOT, OR, AND, NOR, NAND, XOR, and XNOR. The operation principle of these gates is based on the constructive and destructive interferences between the input signal(s) and the control signal. The suggested value of transmission threshold between logic 0 and logic 1 states is 0.25. The suggested value of the transmission threshold achieves all seven plasmonic logic gates in one structure. We use the same structure with the same dimensions at 1550-nm wavelength for all proposed plasmonic logic gates. Although we realize seven gates, in some cases, the transmission of the proposed plasmonic logic gates exceeds 100%, for example, in OR gate (175%), in NAND gate (112.3%), and in XNOR gate (175%). As a result, the transmission threshold value measures the performance of the proposed plasmonic logic gates. Furthermore, the proposed structure is designed with a very small area (400  nm  ×  400  nm). The proposed all-optical logic gates structure significantly contributes to the photonic integrated circuits construction and all-optical signal processing nanocircuits.

1.

Introduction

All-optical devices based on surface plasmon polaritons (SPPs) have been the topic of comprehensive research in recent years. All-optical SPP devices have extensively motivated new actions to overcome the major performance constraints of semiconductor electronic devices, which suffer from ingrained delay and high-heat generation, and to overcome the problem of photonics devices, that is, the diffraction limit. Therefore, the utilization of the aforementioned devices enabled the manipulation of light on a subwavelength scale.1 SPPs are the interaction of electromagnetic waves and the free electrons of metals, propagating on the metal–dielectric or dielectric–metal interfaces.2,3 Different passive and active plasmonic devices, such as nanocavities,4 Bragg reflectors,4 splitters,5 resonators,6 couplers,7 modulators,8 multi/demultiplexers,9 stub waveguides,5 hybrid plasmonic waveguides,10 switches,11,12 and logic gates,1314.15.16.17.18 have been realized so far. On the subject of all-optical logic gates, several studies have been proposed, analyzed, and investigated, for example, single semiconductor optical amplifiers,19 hybrid plasmonic-photonic crystal nanobeam cavities,18 two-photon absorption in silicon waveguides,20 silicon microring resonators,21,22 cross-phase modulation,23 and nanophotonic plasmonics.24

Recently, many all-optical plasmonic structures provided nanoscale logic gates.2526.27.28.29 Each nanologic gate has a different way to realize the functions of the gates, a different number of logic gates, different types of logic gates, different values of resonance frequencies, different geometries, different materials of the structure, and different values of transmission.

In this paper, we offer the largest number of plasmonic logic gates (seven) in the same structure with the same resonance frequency and the same transmission threshold in structure with nanoring resonator and plasmonic nanowaveguides. The plasmonic logic gates that are proposed, analyzed, and realized are NOT, OR, AND, NOR, NAND, XOR, and XNOR. The simulation results are obtained by finite element method (FEM). In future, these devices will be the gateway to the nanophotonic-integrated circuit applications.

The organization of this paper is as follows: Sec. 2 contains the proposed structure layout and theoretical operation concept. In Sec. 3, the simulation results and performance of the proposed all-optical plasmonic logic gates are presented, demonstrated, and discussed. In Sec. 4, a comparison between the proposed work and the previous researches is introduced. Finally, we conclude the suggested work in Sec. 5.

2.

Structure Layout and Theoretical Concept

The proposed structure which realizes the seven all-optical plasmonic gates is shown in Fig. 1.

Fig. 1

The proposed structure for the proposed plasmonic seven logic gates.

JNP_13_1_016009_f001.png

The structure consists of three straight stripes and two nanoring resonators to construct seven logic gates based on the insulator–metal–insulator (IMI) plasmonic waveguides. The dimensions of the proposed structure are 400×400  nm, and the length of the middle and side stripes (Ls) are 400 and 250 nm, respectively. The width (w) of these stripes is 20 nm, the radii of the nanoring resonator (a) and (b) are 25 and 50 nm, respectively, and the coupling distance (d) between the nanoring resonator and the stripes is 7.5 nm.

In our structure, we choose the IMI plasmonic waveguides instead of the metal–insulator–metal (MIM) plasmonic waveguides due to the advantages of IMI over MIM, according to the summarized compression between IMI and MIM in Table 1.

Table 1

Comparison between IMI plasmonic waveguides and MIM plasmonic waveguides.

Sr. No.IMI plasmonic waveguidesMIM plasmonic waveguides
13031.32.33.34.35.36.37.38.39.40More propagation lengthLess propagation length
23031.32.33.34.35.36.37.38.39.40Less confinementMore confinement
33031.32.33.34.35.36.37.38.39.40Less propagation lossMore propagation loss
431,33,37,39More quality factorLess quality factor
531,33,35,39More figure of meritLess figure of merit
641Easy fabricationFabrication is not easy
741Low coupling lossMore coupling loss

In addition to the above comparison, the MIM plasmonic waveguide becomes inefficient to use as logic gates in dimensions <50  nm (width of middle material).30

The materials of the proposed structure are silver and Teflon. In our structure, stripes and two nanorings are represented as silver material, and the remaining part of the structure is a Teflon material as shown in Fig. 1.

All seven proposed plasmonic logic gates have the same dimensions, parameters, and materials in their structures.

In our simulations, Johnson and Christy42 data are used to describe the silver permittivity, and the refractive index of Teflon material is 1.375.43 The resonance wavelength of the nanoring can be determined by Refs. 40 and 44:

(1)

λsp=4πneffD,
where neff is the effective refractive index and D is the bigger diameter of the nanoring. According to Eq. (1), the structure parameters and the type of materials play a role in choosing the resonance wavelength. We focus on the resonance wavelength of 1550 nm, as this wavelength is the best choice in optical communications applications.

The dispersion relation equation for transverse magnetic (TM) mode in the waveguide is given by Refs. 40 and 45:

(2)

εmkd+εdkmtanh(km2w)=0,
where εd is a dielectric constant of the insulator, εm is a dielectric constant of the metal, and w is thin metal thickness:

(3)

kd=(β2+εdk02)1/2(dielectric wave number),

(4)

km=(β2+εmk02)1/2(metal wave number),

(5)

k0=2π/λ(free space wave number),
where β is the propagation constant that is represented by an effective refractive index of the waveguide for SPP, such as depicted in

(6)

neff=β/k0.

Maxwell equations are solved numerically using the two-dimensional (2-D) FEM method; we have used a convolutional perfectly matched layer (CPML) as the absorbing boundary condition of the area under simulation. The structure is excited by a TM-polarized plane wave with electromagnetic field components of Ex, Ey, and Hz.

The proposed structure has four ports, namely the two input ports, control port, and an output port. These ports are decided according to the required plasmonic logic gate. The SPPs are excited with launching a TM-polarized plane wave to the input port(s) and control port. The performance of the seven plasmonic logic gates is measured by two criteria: the first is the transmission of the optical power from the input port(s) and the control port to the output port as a function of wavelength. This can be done by choosing a threshold value of transmission between logic 1 (ON state) and logic 0 (OFF state) at the output in order to decide the type of states (ON or OFF); the value of transmission threshold has been chosen as 0.25 in order to achieve the seven plasmonic logic gates in the same structure.46 The second criterion is the contrast or an extinction ratio between optical power or transmission of the ON and OFF states of the output port, whenever the variance between the optical output power or the transmission of these states is large, the performance of the plasmonic logic gate becomes better. These two criteria are described by Eqs. (7)26 and (8),28 respectively. In our proposed plasmonic logic gates, we are depending on the transmission threshold to decide the desired logic gate:

(7)

T=Pout/Pin(forONandOFFstates of the output port),
where T is the transmission, Pout is the output optical power of the output port in ON state and OFF state, and Pin is the input optical power to the input port (s) and control port. The value of the Pin for each input port(s) and the control port is 1 W:

(8)

ON/OFF  contrast or extinction ratio(dB)=10log(Pout|ONPout|OFF),
where Pout|ON is the output optical power of the output port in case of ON state (logic 1). Pout|OFF is an output optical power of the output port in case of OFF state (logic 0).

When one port from the input port(s) or control port is in ON state, the transmission and output optical power have the same value. In this case, Eq. (8) will become Eq. (9):

(9)

ON/OFF  contrast or extinction ratio(dB)=10log(Pout|ONPout|OFF)=10log(TONTOFF),
where TON is the transmission of optical power from the input port(s), and control port to the output port in case of ON state (logic 1); in other words, TON must be >0.25 for all cases of the proposed plasmonic logic gates in the ON state, and TOFF is the transmission of optical power from the input port(s), and control port to the output port in case of OFF state (logic 0); in other words, TOFF must be <0.25 in all cases of the proposed plasmonic logic gates in the OFF state.

Depending on the shape, size, and parameters of the proposed structure, materials, and refractive index of the chosen materials, the port position, the polarization of incident field and its phase, and the transmission of the optical power is minimized or maximized.

The interaction between stripes and nanorings causes new localized surface plasmon resonances, which are the results of the coupling between the nanorings resonator and the stripes (IMI). Furthermore, since plasmon waves couple strongly only in the near-field regime at very short distances, the coupling distance (d) must be decreased to enable this mechanism to sustain and obtain the highest improvement of the field. Therefore, if the coupling distances increase, the field and the transmission spectrum decrease. According to the obtained results, the optimum coupling distance between the nanorings resonator and the stripes for the proposed structure has been chosen to be 7.5 nm.

On the other hand, the gate function for all proposed plasmonic logic gates is realized by the principle of constructive and destructive interferences between the input signal(s) and the control signal. Thus, the determination of these ports will decide the function of the plasmonic logic gate. The manipulation of the input port(s), control port, and the output port can achieve the required plasmonic logic gate. As we have already explained the reasons, surface plasmons are excited at the wavelength of 1550 nm for the seven proposed plasmonic logic gates.

The principle of the constructive and destructive interferences between the input light signal(s) and the control light signal depends on the phase of the incident light wave and the position of the input port(s) and control port when the other parameters (shape, size, dimensions of the structure, and materials used) remain unchanged.

The constructive interference occurs when the phase of incident wave of the ports (including the control port) as well as the direction of the propagation (depends on position of the ports) are the same, whereas the destructive interference happens when either the phase or the direction of the propagation of the incident wave of the ports are different.

As a result, the phase difference leads to destructive interference between the waves47 according to Eq. (10):48

(10)

m=(4neffdcosθ)/λ,
where m is the interference order as an integer larger than 0, neff is an effective refractive index of the silver material, d is the thickness of the metal material, θ is the phase of the incident wave, and λ is the incident wavelength.

When θ=0  deg, the sign of Eq. (10) is positive; this means the direction of the mode is the same direction of the propagation of the wave. Thus, constructive interference occurs with the other modes that have the same phase. As a result, the transmission will be increased.

When θ=90  deg, Eq. (10) will be equal to zero, and neither constructive nor destructive interference will occur for this mode and the transmission is either increasing or decreasing depending on the other phases of input(s) and control light waves as well as the other parameters.

When θ=180  deg, the sign of Eq. (10) is negative; this means the direction of the mode is in reverse direction of the propagation of the light wave. Thus, the destructive interference occurs with the other modes that have a different phase. As a result, the transmission will be decreased.

3.

Proposed All-Optical Logic Gates

In all seven proposed plasmonic logic gates, the structure is illuminated by a plane wave with a wavelength ranging from 800 to 2000 nm. This illumination is launched to the input port(s) (ON state) and to the control port. To use the proposed structure (Fig. 1) as a structure to the all seven proposed plasmonic logic gates, the input port(s), the control port, and the output port must be determined to give the function of these proposed plasmonic logic gates. The process of choosing these ports for the proposed plasmonic logic gates is done by trial-and-error method to give a better transmission performance and high contrast ratio.

3.1.

Plasmonic NOT Logic Gate

A NOT gate, or inverter, is used to implement the complement concept in switching algebra. Thus, the logic value of the output of a NOT gate is simply the complement of the logic value of its input, according to Figs. 2(a) and 2(b).

Fig. 2

(a) and (b) The conventional symbol of a NOT logic gate and its truth table, respectively. (c) The transmission spectrum of the proposed plasmonic NOT logic gate at different states, according to its truth table. (d) and (e) The electric field distribution (y-component) of logic 1 and logic 0 outputs, respectively.

JNP_13_1_016009_f002.png

To perform a NOT gate in our structure, we choose port 3 as an input port, port 4 as the output port, and port 1 as the control port, whereas port 2 is left as unused (see Fig. 1).

The function of this gate can be realized by the destructive interference between the input signal and the control signal. When the state of the input port is OFF and when the launching light at the wavelength of 1550 nm to the control port with a phase being equal to 180 deg, the state of the output port is ON according to the value of transmission that is 0.2807 (above transmission threshold = 0.25). When the launching light at the wavelength of 1550 nm to the input port and the control port (the state of the input port is ON) with the phase difference between them being 180 deg, then the destructive phenomenon will occur and the state of the output port is OFF according to the value of transmission that is 0.1811 (below transmission threshold = 0.25). The transmission spectrum of the proposed plasmonic NOT logic gate is shown in Fig. 2(c). Figures 2(d) and 2(e) show the electric field distribution (y-component) of logic 1 and logic 0 outputs, respectively. The operation of the proposed plasmonic NOT logic gate is summarized in Tables 2 and 3.

Table 2

Operation of the transmission for the proposed plasmonic NOT logic gate.

Input stateInput portPhase (deg)Control portPhase (deg)TTthresh.Output stateOutput port
Logic 0OFF0ON1800.28070.25Logic 1ON
Logic 1ON0ON1800.18110.25Logic 0OFF

Table 3

Calculation of the contrast ratio for the proposed plasmonic NOT logic gate.

Input optical power/port 1 (W)Input optical power/port 3 (W)Total input optical power (W)Output optical power (W)Output stateContrast ratio (dB)
1010.2807ON1.1
1120.3622OFF

In plasmonic NOT logic gate, the contrast ratio is a negative value and low because the output optical power in OFF state is larger than the output optical power in ON state and the variance between the values of these powers is small, respectively. As a result, the transmission in the ON state is slightly higher than the threshold value and the transmission in the OFF state is slightly lower than the threshold value, which made the contrast ratio low.

3.2.

Plasmonic OR Logic Gate

The output of the OR gate is logic 1 if at least one of the inputs is logic 1 and if all inputs are logic 0, the output is logic 0, according to Figs. 3(a) and 3(b). The OR operator is shown with a plus sign (+) between the variables.

Fig. 3

(a) and (b) The conventional symbol of an OR logic gate and its truth table, respectively. (c) The transmission spectrum of the proposed plasmonic OR logic gate at different states, according to its truth table. (d) and (e) The electric field distribution (y-component) when input ports are OFF and when input ports are ON, respectively.

JNP_13_1_016009_f003.png

To perform an OR gate in our structure, we choose port 1 as input port 1, port 2 as input port 2, port 4 as output port, and port 3 as control port.

In the same manner of the proposed plasmonic NOT logic gate, the function of the proposed OR logic can be realized. Nevertheless, in this gate, it did not need to change the phase shift between the input signal(s) and the control signal in order to get the maximum transmission in three cases. In this gate, the transmission exceeds 100% (1.75) when the two input ports and the control port are both in ON state. The enhancement and amplification of the transmission result from the constructive phenomenon between the input signals (1 and 2) and the control signal because the three signals have the same phase (0 deg). The transmission spectrum of the proposed plasmonic OR logic gate is shown in Fig. 3(c). Figures 3(d) and 3(e) show the electric field distribution (y-component) when input ports are OFF and when input ports are ON, respectively. The operation of the proposed plasmonic OR logic gate is summarized in Tables 4 and 5.

Table 4

Operation of the transmission for the proposed plasmonic OR logic gate.

Input state 1Input state 2Input port 1Phase (deg)Input port 2Phase (deg)Control portPhase (deg)TTthreshOutput stateOutput port
Logic 0Logic 0OFF0OFF0ON00.070.25Logic 0OFF
Logic 0Logic 1OFF0ON0ON00.630.25Logic 1ON
Logic 1Logic 0ON0OFF0ON00.630.25Logic 1ON
Logic 1Logic 1ON0ON0ON01.750.25Logic 1ON

Table 5

Calculation of the contrast ratio for the proposed plasmonic OR logic gate.

Input optical power/port 1 (W)Input optical power/port 2 (W)Input optical power/port 3 (W)Total input optical power (W)Output optical power (W)Output stateContrast ratio
00110.07OFF12.55 dB
12.55 dB
18.75 dB
01121.26ON
10121.26ON
11135.25ON

In Table 5, we note that the contrast ratio is high because the output optical power in ON states is large in comparison with the output optical power in OFF state (variance between Pout|ON and Pout|OFF is large, especially when the two input ports are in ON state). The best contrast ratio of this gate is when the two input ports are in ON state. As a result, the transmission in ON state is high in second and third states and exceeds 100% in forth state.

3.3.

Plasmonic AND Logic Gate

The AND gate produces a logic 1 when all inputs are logic 1, otherwise, the output is logic 0, according to Figs. 4(a) and 4(b). The AND operator is usually shown with a dot between the variables, but it may be implied (no dot).

Fig. 4

(a) and (b) The conventional symbol of an AND logic gate and its truth table, respectively. (c) The transmission spectrum of the proposed plasmonic AND logic gate at different states, according to its truth table. (d) and (e) The electric field distribution (y-component) when input ports are OFF–ON and when input ports are ON, respectively.

JNP_13_1_016009_f004.png

In the AND gate structure, we choose input port 1 as port 1, input port 2 as port 2, output port as port 3, and control port as port 4.

The function of this gate can be realized by the constructive and destructive interferences between the input signal (s) and the control signal. When input ports are in OFF-ON and ON-OFF states (control port is in ON state always), the destructive interference occurs between the input signal and the control signal due to the phase difference (phase of the input signal = 180 deg and phase of control signal = 0 deg), which leads to the reduction in the transmission by 6%. On the other hand, when both input ports are in ON state, the constructive interference occurs between the input signals. As a result, the state of the output port is ON according to the value of the transmission that is 0.72 (above transmission threshold = 0.25). In this case, the transmission does not exceed 100% (72%), although the phase of input signals and the control signal is the same (phase=0  deg), because the control port, namely port 4, has an opposed propagation direction in comparison with the input ports, which causes a destructive interference with the two input signals. The transmission spectrum of the proposed plasmonic AND logic gate is shown in Fig. 4(c). Figures 4(d) and 4(e) show the electric field distribution (y-component) when input ports are OFF-ON and when input ports are ON, respectively. The operation of the proposed plasmonic AND logic gate is summarized in Tables 6 and 7.

Table 6

Operation of the transmission for the proposed plasmonic AND logic gate.

Input state 1Input state 2Input port 1Phase (deg)Input port 2Phase (deg)Control portPhase (deg)TTthreshOutput stateOutput port
Logic 0Logic 0OFF0OFF0ON00.070.25Logic 0OFF
Logic 0Logic 1OFF0ON180ON00.060.25Logic 0OFF
Logic 1Logic 0ON180OFF0ON00.060.25Logic 0OFF
Logic 1Logic 1ON0ON0ON00.720.25Logic 1ON

Table 7

Calculation of the contrast ratio for the proposed plasmonic AND logic gate.

Input optical power/port 1 (W)Input optical power/port 2 (W)Input optical power/port 4 (W)Total input optical power (W)Output optical power (W)Output stateContrast ratio (dB)
00110.07OFF14.89
12.55
12.55
01120.12OFF
10120.12OFF
11132.16ON

In Table 7, we note that the contrast ratio is high because the output optical power in ON states is large when compared with the output optical power in OFF states (variance between Pout|ON and Pout|OFF is large, especially when the two input ports are in OFF state). The best contrast ratio of this gate is when the two input ports are in OFF state. As a result, the transmission in ON state is high.

3.4.

Plasmonic NOR Logic Gate

The NOR gate produces a logic 1 when all inputs are logic 0; otherwise, the output is logic 0, according to Figs. 5(a) and 5(b). The NOR operator is usually shown with a plus sign (+) between the variables and a complement sign covering them.

Fig. 5

(a) and (b) The conventional symbol of a NOR logic gate and its truth table, respectively. (c) The transmission spectrum of the proposed plasmonic NOR logic gate at different states, according to its truth table. (d) and (e) The electric field distribution (y-component) when input ports are OFF and when input ports are ON, respectively.

JNP_13_1_016009_f005.png

In the NOR gate structure, we choose input port 1 as port 2, input port 2 as port 3, output port as port 4, and control port as port 1.

The function of this gate can be achieved by destructive interference between the input signal(s) and the control signal. The first state (OFF–OFF) can be achieved in the same way as the first state of the proposed plasmonic NOT logic gate. In the other three states of the input ports (OFF–ON, ON–OFF, and ON–ON states), the output state is OFF due to the value of transmission is below the transmission threshold. In these three states, the destructive interference occurs due to the phase difference between the input signal(s) and the control signal. The transmission spectrum of the proposed plasmonic NOR logic gate is shown in Fig. 5(c). Figures 5(d) and 5(e) show the electric field distribution (y-component) when the input ports are OFF and when the input ports are ON, respectively. The operation of the proposed plasmonic NOR logic gate is summarized in Tables 8 and 9.

Table 8

Operation of the transmission for the proposed plasmonic NOR logic gate.

Input state 1Input state 2Input port 1Phase (deg)Input port 2Phase (deg)Control portPhase (deg)TTthreshOutput stateOutput port
Logic 0Logic 0OFF0OFF0ON1800.28070.25Logic 1ON
Logic 0Logic 1OFF0ON0ON1800.18110.25Logic 0OFF
Logic 1Logic 0ON0OFF0ON1800.22540.25Logic 0OFF
Logic 1Logic 1ON0ON90ON1800.0450.25Logic 0OFF

Table 9

Calculation of the contrast ratio for the proposed plasmonic NOR logic gate.

Input optical power/port 2 (W)Input optical power/port 3 (W)Input optical power/port 1 (W)Total input optical power (W)Output optical power (W)Output stateContrast ratio
00110.2807ON1.1  dB
2  dB
3.18 dB
01120.3622OFF
10120.4508OFF
11130.135OFF

In Table 9, we note that the contrast ratio is a negative value (first and second values) and low because the output optical power in OFF states (first and second states) is larger than the output optical power in ON state and the variance between the values of these powers is small, respectively. The best contrast ratio of this gate is when the two input ports are in ON state. As a result, the transmission in ON state is slightly higher than the threshold value and the transmission in the OFF state is slightly lower than the threshold value (second and third states).

3.5.

Plasmonic NAND Logic Gate

The NAND gate produces a logic 0 when all inputs are logic 1; otherwise, the output is logic 1, according to Figs. 6(a) and 6(b). The NAND operator is shown with a dot between the variables and a complement sign covering them.

Fig. 6

(a) and (b) The conventional symbol of a NAND logic gate and its truth table, respectively. (c) The transmission spectrum of the proposed plasmonic NAND logic gate at different states, according to its truth table. (d) and (e) The electric field distribution (y-component) when input ports are ON–OFF and when input ports are ON, respectively.

JNP_13_1_016009_f006.png

In the NAND gate structure, we choose input port 1 as port 2, input port 2 as port 3, the output port as port 4, and control port as port 1 (similar to the NOR gate).

The function of this gate can be achieved by the enhancement and suppression interferences between the input signal(s) and the control signal. When the state of the input ports is OFF and when the launching light at the wavelength of 1550 nm to the control port with phase being always equal to 0 deg, the state of the output port is ON according to the value of transmission that is 0.2807 (above transmission threshold = 0.25). In this state, neither constructive nor destructive interference occurs because only one port is in ON state (control port). As a result, the transmission is slightly above the threshold. In the second state (OFF–ON state), the transmission is 0.63 (above transmission threshold = 0.25), which is regarded as a logic 1. In the second state, the transmission does not exceed 100%, although the phase of these ports is equal. This is because the length of stripes of the control port and the input port 2 is unequal. In the third state (ON–OFF state), the amplification to the transmission occurs (transmission = 1.123), which is regarded as a logic 1 also. In this case, the constructive interference occurs between the input signal and a control signal, which leads to the transmission exceeding 100%. In the fourth case (ON–ON), the transmission is 0.045, which is regarded as a logic 0. In this case, destructive interference occurs between input signals and control signal due to the difference in phase. The transmission spectrum of the proposed plasmonic NAND logic gate is shown in Fig. 6(c). Figures 6(d) and 6(e) show the electric field distribution (y-component) when input ports are ON–OFF and when input ports are ON, respectively. The operation of the proposed plasmonic NAND logic gate is summarized in Tables 10 and 11.

Table 10

Operation of the transmission for the proposed plasmonic NAND logic gate.

Input state 1Input state 2Input port 1Phase (deg)Input port 2Phase (deg)Control portPhase (deg)TTthreshOutput stateOutput port
Logic 0Logic 0OFF0OFF0ON00.28070.25Logic 1ON
Logic 0Logic 1OFF0ON0ON00.630.25Logic 1ON
Logic 1Logic 0ON0OFF0ON01.1230.25Logic 1ON
Logic 1Logic 1ON180ON90ON00.0450.25Logic 0OFF

Table 11

Calculation of the contrast ratio for the proposed plasmonic NAND logic gate.

Input optical power/port 2 (W)Input optical power/port 3 (W)Input optical power/port 1 (W)Total input optical power (W)Output optical power (W)Output stateContrast ratio (dB)
00110.2807ON3.12
9.7
12.2
01121.26ON
10122.246ON
11130.135OFF

In Table 11, we note that the contrast ratio is high (second and third states) and low in first ON state. The best contrast ratio of this gate is when the two input ports are in ON–OFF state. As a result, the transmission in ON state is high in the second state and exceeds 100% in the third state, but slightly higher than the threshold value in the first state that makes the contrast ratio is low.

3.6.

Plasmonic XOR Logic Gate

The XOR gate produces a logic 1 output only when both inputs are at opposite logic levels; otherwise, the output is logic 0, according to Figs. 7(a) and 7(b). The XOR operator is usually shown with a circled plus sign () between the variables A and B.

Fig. 7

(a) and (b) The conventional symbol of a XOR logic gate and its truth table, respectively. (c) The transmission spectrum of the proposed plasmonic XOR logic gate at different states, according to its truth table. (d) and (e) The electric field distribution (y-component) when input ports are ON–OFF and when input ports are ON, respectively.

JNP_13_1_016009_f007.png

In XOR gate structure, we choose input port 1 as port 1, input port 2 as port 2, the output port as port 4, and control port as port 3 (similar to the OR gate).

At this plasmonic logic gate (OFF–ON and ON–OFF states), the constructive interference between the input signal and the control signal is not large. However, the transmission = 0.63, which is regarded as logic 1. In the fourth state (ON–ON), destructive interference occurred between the input signals and the control signal due to the difference in the signal phase. Thus, the transmission diminished to 0.087, which is regarded to logic 0. The transmission spectrum of the proposed plasmonic XOR logic gate is shown in Fig. 7(c). Figures 7(d) and 7(e) show the electric field distribution (y-component) when input ports are ON–OFF and when input ports are ON, respectively. The operation of the proposed plasmonic XOR logic gate is summarized in Tables 12 and 13.

Table 12

Operation of the transmission for the proposed plasmonic XOR logic gate.

Input state 1Input state 2Input port 1Phase (deg)Input port 2Phase (deg)Control portPhase (deg)TTthreshOutput stateOutput port
Logic 0Logic 0OFF0OFF0ON00.070.25Logic 0OFF
Logic 0Logic 1OFF0ON0ON00.630.25Logic 1ON
Logic 1Logic 0ON0OFF0ON00.630.25Logic 1ON
Logic 1Logic 1ON180ON90ON00.0870.25Logic 0OFF

Table 13

Calculation of contrast ratio for the proposed plasmonic XOR logic gate.

Input optical power/port 1 (W)Input optical power/port 2 (W)Input optical power/port 3 (W)Total input optical power (W)Output optical power (W)Output stateContrast ratio (dB)
00110.07OFF12.55
6.84
01121.26ON
10121.26ON
11130.261OFF

In Table 13, we note that the contrast ratio is high (first OFF state) and moderate (second OFF state) because the output optical power in ON states is large in comparison with the output optical power in OFF states (variance between Pout|ON and Pout|OFF is large, especially when the two input ports are in OFF state).

3.7.

Plasmonic XNOR Logic Gate

The XNOR gate produces a logic 1 output only when both inputs are in the same logic levels; otherwise, the output is logic 0, according to Figs. 8(a) and 8(b). The XNOR operator is usually shown with a circled plus sign () between the variables and a complement sign covering them.

Fig. 8

(a) and (b) The conventional symbol of an XNOR logic gate and its truth table, respectively. (c) The transmission spectrum of the proposed plasmonic XNOR logic gate at different states according to its truth table. (d) and (e) The electric field distribution (y-component) when input ports are OFF–ON and when input ports are ON, respectively.

JNP_13_1_016009_f008.png

In XNOR gate structure, the input ports, control port, and output port are the same ports of the NOR gate and NAND gate structures.

The function of this gate can be achieved by the constructive and destructive interferences between the input signal (s) and the control signal. The first state (OFF–OFF) can be achieved in the same way as we obtained in the first state of the proposed plasmonic NOT logic gate. In the second and the third states (OFF–ON and ON–OFF), the destructive interference happens between the input signal and control signal due to the difference in phase. Thus, the transmission is less than the threshold and is regarded as logic 0. In the fourth state (ON–ON), the large constructive interference happens between the input signals and the control signal due to the similar phase of these signals (phase=0  deg). This results in amplifying the transmission to be above 100% (175%) and that is regarded as logic 1. The transmission spectrum of the proposed plasmonic XNOR logic gate is shown in Fig. 7(c). Figures 7(d) and 7(e) show the electric field distribution (y-component) when input ports are OFF–ON and when input ports are ON, respectively. The operation of the proposed plasmonic XNOR logic gate is summarized in Tables 14 and 15.

Table 14

Operation of the transmission for the proposed plasmonic XNOR logic gate.

Input state 1Input state 2Input port 1Phase (deg)Input port 2Phase (deg)Control portPhase (deg)TTthreshOutput stateOutput port
Logic 0Logic 0OFF0OFF0ON00.28070.25Logic 1ON
Logic 0Logic 1OFF0ON180ON00.1850.25Logic 0OFF
Logic 1Logic 0ON180OFF0ON00.22540.25Logic 0OFF
Logic 1Logic 1ON0ON0ON01.750.25Logic 1ON

Table 15

Calculation of the contrast ratio for the proposed plasmonic XNOR logic gate.

Input optical power/port 2 (W)Input optical power/port 3 (W)Input optical power/port 1 (W)Total input optical power (W)Output optical power (W)Output stateContrast ratio (dB)
00110.2807ON1.2
2
11.74
10.88
01120.37OFF
10120.4508OFF
11135.52ON

In Table 15, we express four values for contrast ratio: the first and second values are negative and low, because Pout|OFF is larger than Pout|ON and the variance between them is small; and the third and fourth values are high because Pout|ON is larger than Pout|OFF and the variance between them is large. The best contrast ratio of this gate can be obtained when the two input ports are in OFF-ON and ON states. As a result, the transmission in ON state is high and exceeds 100% in the fourth state but slightly higher than the threshold value in the first state, which makes the contrast ratio low and negative.

4.

Comparison between the Proposed Work and the Previous Works

The proposed plasmonic logic gates are compared to the previous papers as depicted in Table 16.

Table 16

Comparison between our proposed plasmonic logic gates and previous papers.

CriteriaThis paperRef. 25Ref. 26Ref. 27Ref. 28Ref. 29
Software program usedFEM-2DFDTD-2-DFDTD-2-DFDTD-2-DFDTD-2-DFDTD-2-D
Proposed structureNanoring IMI plasmonic nanowaveguidesMIM-plasmonic waveguides with nanodisk resonatorMicroring MIM plasmonic waveguidesSquare microring MIM nonlinear plasmonic waveguidesPlasmonic MIM nanowaveguides with slot cavity resonatorRing resonator MIM plasmonic waveguides
Number of proposed logic gates7 gates4 gates1 gate3 gates3 gates2 gates
Proposed logic gatesNOT, OR, AND, NOR, NAND, XOR, and XNORNOT, NAND, XOR, and XNORNOTNOT, AND, and NORNOT, OR, and XORAND and NOR
Realization of proposed plasmonic logic gatesAll proposed plasmonic logic gates are realized in one structureThe proposed plasmonic logic gates are realized in two structuresThe proposed plasmonic logic gate is realized in one structureThe proposed plasmonic logic gates are realized in two structuresThe proposed plasmonic logic gates are realized in one structureThe proposed plasmonic logic gates are realized in one structure
Size400  nm×400  nm1220  nm×1120  nm2.4  μm×3  μm750  nm×900  nm and 1.5  μm×1.8  μm760  nm×600  nmMore than 3  μm×2  μm
Operating wavelength(s)1550 nm525 nm850 nm1535 nm1535 nm944 nm and 999 nm
Dielectric material usedTeflonAirAirSiO2AirAir
Nobel metal usedSilverSilverSilverSilverSilverSilver
Model of description the relative permittivity of the silverJohnson and Christy dataDrude modelDrude modelDrude modelDrude modelDrude model
Performance measuredTransmission and contrast ratioTransmission and contrast ratioTransmissionTransmissionTransmission and contrast ratioTransmission and contrast ratio
Transmission threshold between ON/OFF states0.25% or 25%0.1% or 10%0.2% or 20%0.35% or 35%0.3% or 30%0.5% or 50% or less
Maximum transmission %28.07% at NOT gate
175% at OR gate
72% at AND gate
28.07% at NOR gate
112.3% at NAND gate
63% at XOR gate
175% at XNOR gate
25% at NAND gate
42% at XOR gate
25% at XNOR gate
65.35% at NOT gate70% at NOT gate
70% at NOR gate
90% at AND gate
38% at NOT gate
80% at OR gate
40% at XOR gate
84.06% at AND gate
80.07 at NOR gate
Amplifying of transmissionExists in OR gate, NAND gate, and XNOR gateDoes not existDoes not existDoes not existDoes not existDoes not exist

5.

Conclusion

In this paper, seven plasmonic logic gates have been proposed and realized using 2-D FEM. These gates are NOT, OR, AND, NOR, NAND, XOR, and XNOR. The gates are constructed by the nanoring IMI plasmonic structure. By employing the coupling property between straight stripes and ring resonator waveguides, we can achieve a plasmonic logic gate. By changing the state of the input port (s), the position of the input port(s) and a control port, and the phase of incident light in these ports, we can make the transmission in the output port minimized or maximized according to the required plasmonic logic gate. To give a decision that the proposed plasmonic logic gate is investigating the truth table of one of the logic gates, we have established a threshold value of transmission to distinguish between logic 1 and logic 0 states. The proposed value of transmission threshold is 0.25% or 25%, and choosing this value achieves seven plasmonic logical gates in one structure. Finally, the proposed plasmonic logic gates are considered fundamental building blocks in photonic integrated circuits and all-optical signal-processing systems.

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Biography

Saif H. Abdulnabi received his graduate degree in electrical engineering from Kufa University, Najaf, Iraq, in 2012, and his MSc degree in electrical engineering/electronic and communications from Baghdad University, Baghdad, Iraq, in 2015, where he is currently a PhD student at the Department of Electrical Engineering, University of Baghdad, Baghdad, Iraq, under the supervision of assistant professor Mohammed N. Abbas, PhD.

Mohammed N. Abbas received his BSc and MSc degrees in electrical engineering from the University of Baghdad, Baghdad, Iraq, in 2004 and 2006, respectively, and his PhD in nano science and technology from the National Tsing Hua University, China, in 2011. He is currently an assistant professor at the Department of Electrical Engineering at University of Baghdad. He has published 27 scientific articles and has coauthored one book.

© The Authors. Published by SPIE under a Creative Commons Attribution 4.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.
Saif H. Abdulnabi and Mohammed N. Abbas "All-optical logic gates based on nanoring insulator–metal–insulator plasmonic waveguides at optical communications band," Journal of Nanophotonics 13(1), 016009 (28 February 2019). https://doi.org/10.1117/1.JNP.13.016009
Received: 6 September 2018; Accepted: 14 February 2019; Published: 28 February 2019
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