Automatic Flatness Tester For Very Large Scale Integrated Circuit Wafers

Toyohiko Yatagai; Shigeru Inaba; Hideki Nakano; Masane Suzuki

doi:10.1117/12.7973308

1 August 1984 Automatic Flatness Tester For Very Large Scale Integrated Circuit Wafers

Toyohiko Yatagai, Shigeru Inaba, Hideki Nakano, Masane Suzuki

Author Affiliations +

Optical Engineering, Vol. 23, Issue 4, 234401 (August 1984). https://doi.org/10.1117/12.7973308

Abstract

A high speed automatic flatness analysis system for very large scale integrated circuit wafers has been developed. By using the Fizeau interferometer, a contour map of a silicon wafer is generated, which is then analyzed with a digital image processing system. A special hardware system that performs basic image processing operations, including fringe-peak detection, fringe thinning, fringe-order labeling, local averaging, and so on, was developed. Warpage and undulation of the wafer, which are represented by special indices, are estimated. The surface is not contacted at all during measurement.

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Toyohiko Yatagai, Shigeru Inaba, Hideki Nakano, and Masane Suzuki "Automatic Flatness Tester For Very Large Scale Integrated Circuit Wafers," Optical Engineering 23(4), 234401 (1 August 1984). https://doi.org/10.1117/12.7973308

Published: 1 August 1984

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