Dr. Abhijit Mitra Profile

Dr. Abhijit Mitra

at IIIT Delhi

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Proceedings Article | 2 November 2001 Paper

Real-time performance modeling of (3G) UMTS system

R. Badrinath, Abhijit Mitra, Nishant Sinha, Niloy Mukherjee

Proceedings Volume 4529, (2001) https://doi.org/10.1117/12.447383

KEYWORDS: Signal processing, Telecommunications, Silicon, Computer architecture, Semiconductors, Performance modeling, Networks, Error control coding, Computing systems, Standards development

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Universal Mobile Telecommunications System (UMTS) wireless technologies is a proposed standardization as a part of 3GPP solutions to satisfy IMT-2000 requirements. It is based on wideband CDMA technology. It will provide full coverage and mobility for 144 Kb/s, preferably 384 Kb/s and limited coverage and mobility for 2 Mb/s. It proposes high spectrum efficiency compared to existing systems, handling of different QOS profiles and high flexibility to introduce new service. In this paper, we present our work on modeling of the access stratum (AS) on the User Equipment/Mobile Termination (UE/MT) side of the radio (Uu) interface in accordance with 3GPP UMTS standards. The AS has the following sub-layers: Medium Access Control/Radio Link Control (MAC/RLC), Broadcast Multicast Control (BMC), Packet Data Convergence Protocol (PDCP) and Radio Resource Control (RRC). We have assumed the number of transport channels interfacing the AS MAC sub layer and the physical layer to be eight. The data rates have been assumed to be 384 Kb/s per transport channel both in uplink and downlink. Processing in each sub-layer with corresponding delays and interaction between adjacent sublayers having timing restrictions or rate restrictions have been analyzed. Interaction of the upper sub-layers with the non-access stratum (NAS) and interaction between peer AS sub-layers in the UE and the UTRAN have also been incorporated. A real time priority based scheduler process has been specified to honor the time restrictions e.g. the Transmission Time Intervals (TTI) of the channels. The system has been simulated on Virtual Silicon, a C based SDL tool and evaluated on CR16C architecture family using CR16C debugger, both developed by National Semi Conductor Corp., U.S.A.

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