In the context of short-reach data-center interconnect, such as OIF 400ZR, we study the system impact of bandwidth loss of Silicon Photonics Mach-Zehnder modulators in high-speed coherent modems. As well, we propose a minimum-mean square gradient-descent based method to optimize the compensation of such loss at both transmitter and receiver signal processing finite-impulse response filters. The method improves required-optical signal to noise ratio (ROSNR), under realistic hardware restrictions such as implementation noise and clock jitters at data converters, by 0.5 dB compared to fully pre-compensating the frequency response. Other advantages, such as lower power consumption, are highlighted as well.
In the context of standardized 400ZR, we study the adjacent channel power ratio (ACPR) as a measure for quantifying the impact of pluggables in flexible-grid dense wavelength division multiplexing (DWDM) networks. Using Monte- Carlo simulations, the ACPR is calculated under standardized roll-off factors for a dual-polarization 16QAM channel at 59.8GBaud. The ACPR is shown to adequately represent the impact of linear cross-talk as a function of channel spacing and channel power. From 75GHz (DWDM) to 59GHz (Super-Nyquist) optical transmission, we report a universal approach for specifying the penalties of flexible-grid pluggables on a channel’s required signal-to-noise ratio (SNR) and timing recovery.
In this paper, a three-stage packet switch architecture is implemented consisting of a reconfigurable optical center stage surrounded by two electronic buffering stages grouped into sectors to ease contention. A Flexible Bandwidth Provision algorithm is used to change the configuration of the optical center stage to form the requested bandwidth desired by incoming traffic. The switch is modeled by a bipartite graph built from the service matrix. The bipartite graph is decomposed by solving an edge-coloring problem and the resulting permutations are used to configure the central stage removing the requirement for a per-time slot scheduler.
Flexible Bandwidth Provision (FBP) algorithm requires dynamically reconfigurable technology readily available in programmable logic devices. The designed packet switch being a collection of discrete entities is most easily implemented on separate programmable logic devices forming electronic “islands” interconnected by photonics technology. The demonstrator itself contains 64 inputs and 64 outputs with reconfigurable central stage crossbars. The switch is a collection of input and output sectors each implemented on a single FPGA. Each sector is an 8 x 8 sub-switch with shared buffer memory. The interface between the sectors and the central stage will use VCSEL technology for O-E-O conversion. The input sectors together with the central stage form the adaptive portion of the switch configured by an embedded soft-core processor implementing the FBP algorithm of which is entity are located on an Ethernet local area network.
This switching architecture has also been simulated and results show that this architecture result in a dramatic reduction of complexity, at the price of only a modest spatial speed-up (<2).