Design rules are geometric constraints imposed on IC layout to ensure products can be manufactured at an acceptable yield. Designs are required to pass sign-off design rule check (DRC) before tape-out. Foundries rely on DRC to ensure designs they accept are manufacturable. DRC runsets must be accurate, complete, and reliable. DRC runset qualification is critical in technology node deployment and maturation. The number, complexity and variation of design rules grow dramatically with advancing technology nodes. This increases the QA challenge to ensure quality and accuracy of runsets and their interdependent rule operations. Traditional methods of migrating previous node QA patterns, manually crafting new testcases, and targeted-pattern generation leave gaps in advanced process node qualification coverage. We deploy a novel synthetic layout generation approach to produce large varieties of complex layouts with high design space coverage to thoroughly qualify runsets, make runset improvements and release quality PDKs. We employ guided random Monte Carlo layout generation with user-defined layout construction rules. User-defined rules inform DRC requirements and assign weighted priorities to guide layout design styles. We generate stress DR layouts and high pattern coverage, with DRC-clean patterns and with deliberate DRC violations, to validate expected DRC results and exercise entire rule decks. In this paper, we show how Synthetic Layout Generation is integrated into runset QA flows, automatically generating stress DR conditions that manual efforts often miss, expand layout pattern space coverage, and improve runset execution coverage leading to higher quality on-time PDK development, qualification, and release.