Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly  and has, therefore, become a standard DFM procedure . Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.
In nano-meter scale Integrated Circuits, via fails due to random defects is a well-known yield detractor, and via
redundancy insertion is a common method to help enhance semiconductors yield. For the case of Self Aligned Double
Patterning (SADP), which might require unidirectional design layers as in the case of some advanced technology nodes,
the conventional methods of inserting redundant vias don’t work any longer. This is because adding redundant vias
conventionally requires adding metal shapes in the non-preferred direction, which will violate the SADP design
constraints in that case. Therefore, such metal layers fabricated using unidirectional SADP require an alternative method
for providing the needed redundancy.
This paper proposes a post-layout Design for Manufacturability (DFM) redundancy insertion method tailored for the
design requirements introduced by unidirectional metal layers. The proposed method adds redundant wires in the
preferred direction - after searching for nearby vacant routing tracks - in order to provide redundant paths for electrical
signals. This method opportunistically adds robustness against failures due to silicon defects without impacting area or
incurring new design rule violations. Implementation details of this redundancy insertion method will be explained in
One known challenge with similar DFM layout fixing methods is the possible introduction of undesired electrical
impact, causing other unintentional failures in design functionality. In this paper, a study is presented to quantify the
electrical impacts of such redundancy insertion scheme and to examine if that electrical impact can be tolerated. The
paper will show results to evaluate DFM insertion rates and corresponding electrical impact for a given design utilization
and maximum inserted wire length. Parasitic extraction and static timing analysis results will be presented. A typical
digital design implemented using GLOBALFOUNDRIES 7nm technology is used for demonstration.
The provided results can help evaluate such extensive DFM insertion method from an electrical standpoint.
Furthermore, the results could provide guidance on how to implement the proposed method of adding electrical
redundancy such that intolerable electrical impacts could be avoided.