Below the 28nm node the difficulty of using subresolution assist features (SrAFs) in OPC/RET schemes increases substantially with each new device node. This increase in difficulty is due to the need for tighter process window control for smaller target patterns, the increased risk of SrAF printing , and also the increased difficulty of SrAF mask manufacture and inspection. Therefore, there is a substantially increased risk of SrAFs which violate one or more manufacturability limits.
In this paper, we present results of our work to evaluate methods to pre-characterize designs which are likely to become problematic for SrAF placement. We do this by evaluating different machine learning methods, inputs and functions.
A hybrid multi-step method for Sub-Resolution Assist Feature (SRAF) placement is presented. The process window, characterized by process variation bands (PV-bands), is subjected to optimization. By applying a state-of-the-art advanced pattern matching based approach, the SRAF placement is optimized to maximize the process window. Due to the complexity of building a complete Rule-Based SRAF (RBSRAF) solution and the performance limitation of the Model-Based SRAF solution (MBSRAF), the hybrid pattern based SRAF reduces the complexity and improves performance. In this paper, the hybrid pattern-based SRAF algorithm and its implementation, as well as testing results, are discussed with respect to process window and performance.
To ensure a high patterning quality, the etch effects have to be corrected within the OPC recipe in addition to the traditional lithographic effects. This requires the calibration of an accurate etch model and optimization of its implementation in the OPC flow. Using SEM contours is a promising approach to get numerous and highly reliable measurements especially for 2D structures for etch model calibration. A 28nm active layer was selected to calibrate and verify an etch model with 50 structures in total. We optimized the selection of the calibration structures as well as the model density. The implementation of the etch model to adjust the litho target layer allows a significant reduction of weak points. We also demonstrate that the etch model incorporated to the ORC recipe and run on large design can predict many hotspots.
A two-step full-chip simulation method for optimization of sub-resolution assist feature placement in a random
logic Contact layer using ArF immersion Lithography is presented. Process window, characterized by depth of
focus (DOF) , of square or rectangular target features is subject to optimization using the optical and resist effects
described by calibrated models (Calibre ®
nmOPC, nmSRAF simulation platform). By variation of the assist
feature dimension and their distance to main feature in a test pattern, a set of comprehensive rules is derived
which is applied to generate raw assist features in a random logic layout. Concurrently with the generation of
the OPC shapes for the main features, the raw assist feature become modified to maximize process window and
to ensure non-printability of the assist features. In this paper, the selection of a test pattern, the generation of
a set of "golden" rules of the raw assist feature generation and their implementation as well as the assist feature
coverage in a random logic layout is presented and discussed with respect to performance.
A dynamic feedback controller for Optical Proximity Correction (OPC) in a random logic layout using ArF
immersion Lithography is presented. The OPC convergence, characterized by edge placement error (EPE), is
subjected to optimization using optical and resist effects described by calibrated models (Calibre®
simulation platform). By memorizing the EPE and Displacement of each fragment from the preceding OPC
iteration, a dynamic feedback controller scheme is implemented to achieve OPC convergence in fewer iterations.
The OPC feedback factor is calculated for each individual fragment taking care of the cross-MEEF (mask error
enhancement factor) effects. Due to the very limited additional computational effort and memory consumption,
the dynamic feedback controller reduces the overall run time of the OPC compared to a conventional constant
feedback factor scheme. In this paper, the dynamic feedback factor algorithm and its implementation, as well
as testing results for a random logic layout, are compared and discussed with respect to OPC convergence and