UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting
pioneers in the industry who were searching for the finest patterns.
We have been focused on the resolution improvement in NIL template making with a 100keV acceleration voltage
spot beam EB writer process, and have established a template making process to meet the requirements of the pioneers.
Usually such templates needed just a small field (several hundred microns square or so).
Now, for several semiconductor devices, the UV NIL is considered not only as a patterning solution for R&D
purpose but eventually as a potential candidate for production, and instead of a small field, a full chip field mask is
required. Although the 100kV EB writers have excellent resolution capability, they are adopting spot beams (SB) to
generate the pattern and have a fatally low throughput if we need full chip writing.
In this paper, we are focusing on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X
photomask manufacturing. The 50keV VSB writers can generate full chip pattern in a reasonable time, and by choosing
the right patterning material and process, we achieved resolution down to 28nm.
UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns.
We have been focused on the resolution improvement in mask making, and with a 100kV acceleration voltage EB writer process, we have achieved down to 18nm resolution, and have established a mask making process to meet the requirements of the pioneers. Usually such masks needed just a small field (several hundred microns square or so).
Now, UV NIL exploration seems to have reached the step of feasibility study for mass production. Here, instead of a small field, a full chip field mask is required, though the resolution demand is not as tough as for the extremely advanced usage. The 100kV EB writers are adopting spot beams to generate the pattern and have a fatally low throughput if we need full chip writing.
In this work, we focused on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50kV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we could achieve resolution down to 32nm. Our initial results of 32nm class NIL masks with full chip field size will be shown and resolution improvement plan to further technology nodes will be discussed.
NIL (nano-imprint lithography) is expected as one of the lithographic candidates for 32nm node and beyond.
Recently, the small line edge roughness (LER) as well as the potentially high resolution that will ensure no-OPC mask
feature is attracting many researchers. However, the NIL needs 1X patterns on template and a transit from 4X to 1X is a
big and hard technology jump for the mask industry. The fine resolution pattern making on the template is one of the
most critical issues for the realization of NIL.
In this paper, as a continuation of our previous works1-5, we have achieved further resolution by optimizing
the materials, their thicknesses, the developing and the etching processes, as well as the writing parameters of the
100keV SB (spot beam) writer. At the best resolved point on the template, resolutions down to hp (half pitch) 18nm on
dense line patterns, hp20nm on dense hole patterns, and hp26nm on dense dot patterns were confirmed. Concerning
stable pattern resolution over a certain field area, we evaluated pattern resolution through over a 250um square area,
which we think would be adequate for initial imprint tests. For the 250μm square area, we confirmed pattern resolution
of hp24nm for dense line patterns and hp32nm for dense hole patterns.
In addition, we have studied resolution limit of the 50keV VSB (variable shaped beam) photomask
production writing tools, which have been commonly used tools in the 4X photomask manufacturing for larger field size
patterning. Materials, process conditions and parameters acquired through the 100keV SB process were implanted, and
we could fabricate templates with hp32nm dense line patterns, with acceptable full chip uniformity and writing time.
We also studied the imprint capability, and fabricated a template with fine features and imprinted it onto a
wafer. As a result, we could transfer hp24nm dense line patterns, hp24nm dense hole patterns, and hp32nm dense dot
patterns onto the wafer.
EUV mask pattern inspection was investigated using current DUV reticle inspection tool. Designed
defect pattern of 65nm node and 45nm node were prepared. We compared inspection sensitivity
between before buffer etch pattern and after buffer etch pattern, and between die to die mode and die to
database mode. Inspection sensitivity difference was not observed between before buffer etch pattern
and after buffer etch pattern. In addition to defect inspection, wafer print simulation of program defect
was investigated. Simulation results were compared to inspection result. We confirmed current DUV
reticle inspection tool has potential for EUV mask defect inspection.
Absorber layer patterning process for low reflectivity tantalum boron nitride (LR-TaBN) absorber layer and
chromium nitride (CrN) buffer layer were improved to satisfy high resolution pattern and high level critical dimension
(CD) control. To make 100nm and smaller pattern size, under 300nm resist thickness was needed because of resist
pattern collapse issue. We developed absorber layer dry etching process for 300nm thickness resist. Absorber layer
patterning was done by a consequence of carbon fluoride gas process and chlorine gas process. We evaluated both gas
processes and made clear each dry etching character. Sufficient resist selectivity, vertical side wall, good CD control and
low buffer layer damage were obtained. Then, we evaluated how buffer layer dry etching affects EUV reflectivity.
Finally, we evaluated EUV mask pattern defect inspection and defect repair. Sufficient contrast of mask pattern image
and good repair result were obtained using DUV inspection tool and AFM nano-machining tool, respectively.
Dry etch process of ASET developed EUV blank was evaluated. ASET blank used TaGeN for absorber layer and Cr for buffer layer. CF4 gas process and Cl2 gas process were evaluated for TaGeN absorber layer dry etching. Because of advantages of small buffer layer damage and etching stability, CF4 gas process was selected as our standard process for TaGeN etching. Cl2 and O2 mixture gas was used for Cr buffer layer dry etching. After buffer layer dry etching, EUV reflectivity and wafer print were tested. AFM nano-machining was applied to absorber layer defect repair. Repair results were evaluated using SEM, AFM and wafer print test. EUV mask fabrication process was also developed for commercial EUV blank.
For the coming technology nodes, lithography options that use 1X masks are becoming practical candidates. Especially the nano-imprint lithography (NIL) is expected as one of the candidates for 32nm node and below, because of its potential low lithography cost. Naturally, 1X masks require features finer than those on today's 4X masks, and for mask making this means a big and hard technology jump. From the mask making point of view, even the 1X mask is still a candidate, it would be a technology driver in terms of patterning process development for the coming nodes.
In this paper, we focused on the NIL mold (or mask) making evaluation. Among the important factors dominating the resolution of the mask making process, we studied particularly on the resist and the dry etch. We found that with tools currently used in the commercial mask shops today, and by modification of resists, we could achieve 30nm isolated spaces and 50nm dense lines and holes.
We also discuss about our initial results of mask EB writing method evaluation. We found that, to improve the resolution further, the implementation of high resolution EB tools into the mask manufacturing line is inevitable to made molds for 32nm or 22nm technology nodes.
Increase of cost and long turn-around-time (TAT) are becoming hot topics for advanced photomasks. Especially, in the small volume production such as SoC and pilot production, the mask cost and TAT are becoming an important issue for the semiconductor industry. To get rid of these issues, we propose the R-mask (resist shade mask) concept, and in this paper, we will focus on the fabrication techniques of the R-mask. The essential of the R-mask is the simplification of mask fabrication and inspection process. A newly developed e-beam resist, which is able to shield the KrF light, is used as the mask pattern material instead of the chrome. Pellicle is mounted immediately after the mature development process, so that defect density could be reduced. Furthermore, the R-mask concept omits mask cleaning and repair process. We evaluated the newly developed e-beam resist from the standpoint of applicability to mask manufacturing, and we successfully made an R-mask for 180nm metal layer pattern with the new resist. In this paper the process performance of resist is reported.