Pattern placement error (PPE) of device pattern and overlay mark does not necessarily coincide. So it is important to measure PPE of device pattern accurately for optimizing overlay mark design. But it has been hard. To resolve this problem a new method has been developed.
As a device pattern via chain pattern is used that consists of 1st metal, via, and 2nd metal layers. The electrical resistance is almost determined by the contact area of metal and via which depend on their mutual overlay. Since the resistance is inversely proportional to the contact area, the resistance changes sharply as the overlay error becomes large. With the characteristic the fine measurement accuracy of about 1nm has been gotten.
We evaluate the relation of PPE between the device pattern and various types of overlay marks such as box in box mark and device size-segmented mark on 65nm node Cu interconnect. As a result, it has been confirmed that the device size-segmented mark most represents the PPE of device pattern at various aberrations.
We developed a process monitoring system that calculates the effective dose and focus of device wafers using an overlay metrology tool. The effective dose is monitored by measuring the overall width of the fine line-and-space (LS) patterns, the duty ratio of which gradually changes. The effective focus is monitored by measuring the line-end-shortening of the printed line patterns. We used newly designed focus-monitor marks along with conventional LS marks for line-end-shortening. The new marks, which can be measured as an overlay, showed better reproducibility than conventional marks. We calculated the focus shifts caused by variations in the layer structure of device wafers by measuring shots that had been intentionally defocused. Using the defocused shots, we were able to improve the accuracy of our focus-shift calculations. The focus monitor displayed various properties depending on the measurement methods, the design of the marks, and device-layer conditions. Therefore, the mark design must be optimized to each device layer. We demonstrated the accuracy of this monitoring system by applying it to the various layers in a 65-nm-node Cu/low-k interconnect process.