A heuristic optimization approach has been developed to optimize SRAF (sub resolution assist feature) placement rules for advanced technology nodes by using a genetic algorithm. This approach has demonstrated the capability to optimize a rule-based SRAF (RBSRAF) solution for both 1D and 2D designs to improve PVBand and avoid SRAF printing. Compared with the MBSRAF based POR (process of record) solution, the optimized RBSRAF can produce a comparable PVBand distribution for a full chip test case containing both random SRAM and logic designs with a significant 65% SRAF generation time reduction and 55% total OPC time reduction.
Challenges in block levels due to the dilemma of cost control and under-layer effects have been addressed in several papers already, and different approaches to solve the issue have been addressed. Among the known approaches, developable BARC and under-layer aware modeling are the most promising. However, in this paper we will discuss and explain the limitation inefficiency of both methods. In addition, as more block levels are employing etching step, the under-layer dependent etch behavior that we see in some of the block levels is also discussed. All these place great challenges for block level process development. We discuss here possible solutions/improvements including: developable BARC (dBARC) thickness optimization for specific under layers; Simplified model based corrections for lith and etch. This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533
Model based optical proximity correction (MB-OPC) is essential for the production of advanced integrated circuits
(ICs). As the speed and functionality requirements of IC production necessitate continual reduction of the critical
dimension (CD), there is a heightened demand for more accurate and sophisticated OPC models.
The OPC is applied to the design data through a rule deck. The parameters in this rule deck, which we will call
"setup parameters", describe the fundamental way in which the OPC engine will distinguish which edges to move,
their restrictions to movement, and how the targets for the OPC are chosen. The optimization of these setup
parameters, by customizing how the OPC engine should treat specific designs, is an essential step that is performed
in order to maximize the benefit of the OPC model. Improper or deficient selection of the setup parameters strongly
affects the success or failure of the OPC model and engine to achieve the desired design shapes.
In this paper, the ability of setup parameter optimization to compensate for a weak OPC model, or conversely, how
inadequately selected setup parameters can cause a very good OPC model to function poorly is investigated. Our
approach is to use two OPC models: a good OPC model and a weak OPC model. The setup parameters will be
optimized for the weak OPC model to investigate any improvements in the overall OPC performance. Alternatively,
setup parameters chosen poorly will be used with the good OPC model to see how this will adversely affect the OPC
performance. A comparative study will be carried out in order to fully understand the effect of setup file parameters
on the overall OPC performance.
The general goal of this study is to help the OPC modelers and setup parameters optimizers to improve the quality
and performance of the OPC solution and weigh the tradeoffs associated with different OPC solution choices.
Conference Committee Involvement (1)
18 September 2007 | Monterey, California, United States