In recent years semiconductor manufacturers have increasingly employed deep through-silicon via (TSV) at the front end of line (FEOL) process steps, combined with using an increased number of multilevel, three-dimensional (3D) layers with different material stack at the back end of line (BEOL) process steps. This increased usage results in enhanced requirements for 3D feature characterization during the process development steps, as well as with monitoring and failure analysis during production.
Traditionally, deep TSV features during the FEOL are analyzed by cleaving (breaking) the wafers and observing the cross section. At the BEOL, focused ion beam (FIB) cross section and etch back or chemical mechanical polishing (CMP) of layer-by-layer are used to characterize the 3D multilevel layers. Both methods result in a slow turnaround time (TAT), but most importantly, cross section analysis only gives two-dimensional (2D) information about 3D multilevel structure and can miss abnormalities. Etch back or CMP has relatively low quality, accuracy, and repeatability and results in full wafer scrap.
Inline Xe plasma FIB (PFIB) has become an important tool for 3D feature characterization and failure analysis in the chip manufacturing production line. Layer-by-layer excavation (also known as delayering) of a specific site provides enhanced metrology and reconstruction of complete 3D features. Thus, manufacturers can identify process abnormalities of the complete structure. Moreover, inline delayering, combined with cross sectioning of specific sites, enhances the TAT. The wafer can return to production for further analysis, and manufacturers can study the effects on different steps.