PROCEEDINGS ARTICLE | September 16, 2005

Proc. SPIE. 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV

KEYWORDS: Digital signal processing, Logic, Clocks, Field programmable gate arrays, Computer simulations, Signal processing, Mathematics, Computer aided design, Algorithm development, Algorithms

Today FPGAs are used in many digital signal processing applications. In order to design high-performance area efficient DSP pipelines various arithmetic functions and algorithms must be used. In this work, FPGA-based functional units for Cosine, Arctangent, and the Square Root functions are designed using bipartite tables and iterative algorithms. The bipartite tabular approach was four to 12 times faster than the iterative approach but requires 8-40 times more FPGA hardware resources to implement these functions. Next, these functions along with the FPGA hardware multipliers and a reciprocal bipartite table unit are used for hardware rectangular-to-polar and polar-to-rectangular conversion macro-functions. These macro-functions allow for a 7-10 times performance improvement for the high-performance pipelines or an area reduction of 9-17 times for the low cost implementations. In addition, software tool to design FPGA based DSP pipelines using the Cosine, Sine, Arctangent, Square Root, and Reciprocal units with the hardware multipliers is presented.