Reduction of power dissipations in CMOS circuits needs to be addressed for portable battery devices. Selection of appropriate transistor library to minimise leakage current, implementation of low power design architectures, power management implementation, and the choice of chip packaging, all have impact on power dissipation and are important considerations in design and implementation of integrated circuits for low power applications. Energy-efficient architecture is highly desirable for battery operated systems, which operates in a wide variation of operating scenarios. Energy-efficient design aims to reconfigure its own architectures to scale down energy consumption depending upon the throughput and quality requirement. An energy efficient system should be able to decide its minimum power requirements by dynamically scaling its own operating frequency, supply voltage or the threshold voltage according to a variety of operating scenarios. The increasing product demand for application specific integrated circuit or processor for independent portable devices has influenced designers to implement dedicated processors with ultra low power requirements. One of these dedicated processors is a Fast Fourier Transform (FFT) processor, which is widely used in signal processing for numerous applications such as, wireless telecommunication and biomedical applications where the demand for extended battery life is extremely high. This paper presents the design and performance analysis of a low power shared memory FFT processor incorporating dynamic voltage scaling. Dynamic voltage scaling enables power supply scaling into various supply voltage levels. The concept behind the proposed solution is that if the speed of the main logic core can be adjusted according to input load or amount of processor's computation "just enough" to meet the requirement. The design was implemented using 0.12 μm ST-Microelectronic 6-metal layer CMOS dual- process technology in Cadence Analogue Environment.
This paper presents a fully differential ultra low power successive approximation (SA) Analog-to-digital converter (ADC) for biomedical application. In order to reduce the system power consumption, the building block components of the SA ADC architecture has been optimised. In addition, the ADC the input voltage swing is scaled down to in order to reduce the slope gain error and the nonlinearity errors. The SA ADC has been implemented in Cadence Analog Design Environment using 0.18-micron CMOS technology. The designed SA ADC operates at a sampling rate of 200S/s at 3V power supply and consumes only 12µW of power at this frequency. The ADC standby power consumption is less than 1µW. The designed 16-bit ADC occupies an area of 0.1 mm<sup>2</sup> and is the smallest in size among its 16-bit counter parts reported in the literature. The proposed 16-bit ADC achieves the differential-non-linearity (DNL) and integral-non-linearity errors (INL) of ± 0.5 LSB and ± 0.3 LSB respectively.
The two main sources of power dissipation in CMOS circuits are dynamic and static power dissipation. Static power dissipation is due to leakage current when the transistor is normally off. The improvement in technology scaling has introduced very large subthreshold leakage current, therefore careful design techniques are very important in order to reduce subthreshold leakage current for low power design. Leakage current occurs in both active and standby modes. It is recommended to switch off the leakage current when the circuit is in standby mode, however it is not always possible to shut off the leakage current completely during this mode. Unlike gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low-<i>V<sub>t</sub></i> transistors for its high-speed capability and High-<i>V<sub>t</sub></i> transistors for very small leakage current. Multi-Threshold CMOS (MTCMOS) and Variable-Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design. Ideally the larger the threshold level the lower the leakage current, however, one must decide the optimum value of threshold level between the power switch (High-<i>V<sub>t</sub></i> devices) and (Low-<i>V<sub>t</sub></i> devices), as recovery delay tends to increase in higher threshold level. The full paper will discuss the design and performance of SRAM implemented using MTCMOS and VTCMOS biasing techniques. An improved sensing amplifier in the memory cell was incorporated to enhance the circuit performance.
Proc. SPIE. 5649, Smart Structures, Devices, and Systems II
KEYWORDS: Digital signal processing, Clocks, Application specific integrated circuits, Error analysis, Control systems, Data acquisition, Relays, Signal generators, Electronic filtering, Signal detection
This paper presents the application specific integrated circuit (ASIC) implementation of an intelligent controller for a reconfigurable data acquisition (DAQ) system. The DAQ system is employed in a digital relay for power system protection application. The controller is the intelligence behind the reconfigurable architecture. It continuously monitors the voltages and currents to detect the appearance of an abnormal condition on the power transmission network. Then it will send signals to adjust DAQ system sampling speed and filter cut-off frequency for properly detecting the fault location and properly analysing the fault. A novel approach to determine the line impedance angle has been proposed. This approach eliminates the square-root and arc-tan operations to reduce the cost of the semi-custom ASIC implementation of the intelligent controller. Analysis revealed that the intelligent controller achieved a maximum operating frequency of 100MHz, with 10ns critical path delay. The controller core utilises an area of 1.9mm<sup>2</sup>.
There has been significant growth in the wireless market where new applications are accompanied with strict design goals such as low cost, low power dissipation and small form factor. Large capacity and range for new applications are the driving force for development of new standard such as third generation mobile system (3G). Recent research results show that the development that was not possible with current IC technology is made possible with MicroElectroMechanical Systems (MEMS) technology. Significant amount of research is taking place to replace the off-chip components with on-chip components to design a high performance receiver front end. The passive components such as switches, capacitors and inductors are integral part of RF front end. High quality (Q) inductors are used to design RF front-end components such as voltage-controlled oscillator (VCO) and low noise amplifier (LNA). However, they are the bottleneck in achieving the on-chip optimum components, because of Q factor dependence on parasitic effects, limiting the performance. In recent research publications different on-chip inductor structures such as coil, polygon, rectangular and stacked configurations have been suggested and used to implement high value of inductance. In this paper design and implementation issues of MEMS inductor are presented. The paper is divided in two sections, the first section presents the role of MEMS based passive components and second section presents design issues, implementation and analysis of different MEMS based inductors.
The new MEMS technology has made a major impact on design of RF components. The results that were not possible with current IC technology are made possible with MEMS technology. Researchers are working to replace the off-chip components with on-chip components so as to achieve a single chip receiver. The high Q inductors and capacitors required for designing RF components are the bottleneck in achieving the single chip receiver. The main advantage of direct conversion architecture is fewer components are required for implementations, but there are certain design issues that must be taken care for these implementations to be successfully achieved. In this paper, MEMS components used within RF systems is analysed. The VCO is the most difficult block of RF front-end design having large impact on system performance; so stringent requirements are imposed on VCO phase noise performance. A typical range of MEMS component values are used to design and implementation the VCO.
A control unit has been proposed, which is used to reconfigure a pipeline ADC for a mobile terminal receiver that can drastically reduce the power dissipation dependent on adjacent channel interference. The proposed design automatically scales the word length by monitoring the quantization noise along the in-band and out-of-bands powers in the UTRA-TDD spectrum. The new ADC performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. Results show that by using the control unit to reconfigure the ADC, up to 88% power dissipation could be saved, when compared to a fixed 16 bits ADC without the use of the control unit. This will prolong talk and standby time in a moble terminal.