It is known that the influence of line edge roughness (LER), formed during lithography and plasma etching processes, on the MOSFET characteristics becomes more critical with downscaling of the device. This is because LER and line width roughness do not scale down with the dimensions of the devices. High values of LER can lead to increase of current leakage and voltage fluctuations and hence cause degradation of circuit performance and yield. However the gate LER is hard to measure by conventional tools. Therefore reliable LER metrology approach is required. In this study conventional AFM technique is used to estimate LER.