As the semiconductor industry continues to strive towards high volume manufacturing for EUV, flatness specifications for photomasks have decreased to below 10nm for 2018 production, however the current champion masks being produced report P-V flatness values of roughly ~50nm. Write compensation presents the promising opportunity to mitigate pattern placement errors through the use of geometrically adjusted target patterns which counteract the reticle’s flatness induced distortions and address the differences in chucking mechanisms between e-beam write and electrostatic clamping during scan. Compensation relies on high accuracy flatness data which provides the critical topographical components of the reticle to the write tool. Any errors included in the flatness data file are translated to the pattern during the write process, which has now driven flatness measurement tools to target a 6σ reproducibility <1nm. Using data collected from a 2011 Sematech study on the Alpha Demo Tool, the proposed methodology for write compensation is validated against printed wafer results.
Topographic features which lack compensation capability must then be held to stringent specifications in order to limit their contributions to the final image placement error (IPE) at wafer. By understanding the capabilities and limitations of write compensation, it is then possible to shift flatness requirements towards the “non-correctable” portion of the reticle’s profile, potentially relieving polishers from having to adhere to the current single digit flatness specifications.
Due to the impact on image placement and overlay errors inherent in all reflective lithography systems, EUV reticles
will need to adhere to flatness specifications below 10nm for 2018 production. These single value metrics are near
impossible to meet using current tooling infrastructure (current state of the art reticles report P-V flatness ~60nm). In
order to focus innovation on areas which lack capability for flatness compensation or correction, this paper redefines
flatness metrics as being “correctable” vs. “non-correctable” based on the surface topography’s contributions to the final
IP budget at wafer, as well as whether data driven corrections (write compensation or at scanner) are available for the
reticle’s specific shape.
To better understand and define the limitations of write compensation and scanner corrections, an error budget for
processes contributing to these two methods is presented. Photomask flatness measurement tools are now targeting 6σ
reproducibility <1nm (previous 3σ reproducibility ~3nm) in order to drive down error contributions and provide more
accurate data for correction techniques. Taking advantage of the high order measurement capabilities of improved
metrology tooling, as well as computational capabilities which enable fast measurements and analysis of sophisticated
shapes, we propose a methodology for the industry to create functional tolerances focused on the flatness errors that are
not correctable with compensation.