Shrinking design rule coupled with complex device geometries and introduction of new materials in the manufacturing of today’s semiconductor devices generate inherent device weak points which in turn give rise to mechanisms that result in yield impacting defects. The development and introduction of finFET has helped considerably in the quest to further shrink design rule. However, the design and complex manufacturing process involved in producing these high performance finFET devices bring with it a whole new class of defects that have considerable impact on device performance and yield. Some of these defects are buried beneath the wafer surface and are very difficult to detect. They are often missed by optical inspection, only to cause fails at final testing. Failure analysis (FA) then becomes the only means by which they are uncovered. FA is a destructive methodology and its benefits are realized only after the fact. Unlike FA, e-Beam inspection is non-destructive. e-Beam uses electron optics and has a unique ability to detect buried defects electrically by voltage contrast (VC) between a defective structure and its reference. As process window gets tighter and tighter process margin becomes difficult to predict. In this work, e-Beam inspection and overlay data is used to identify process weakness regions on wafer to predict fails and help optimize process and improve yield.
The semiconductor industry current standard of focus setup and control can be improved by the implementation of diffraction-based focus (DBF) marks and their applications. Determining best focus per scanner/reticle/device/layer (SRDL) combination is currently done by exposing a focus/energy matrix (FEM) wafer and examining CD features. The drawback of this process of record (POR) method is that the accuracy is greatly influenced by inter- and intra-field effects, focus step size, and machine accuracy. However, DBF marks do not suffer from these drawbacks because they are measured on product and close to the CD features. Experiments confirm that when comparing Bossung curves on each scanner, the wafer-to-wafer variation is much lower using DBF. The setup time and accuracy of new SRDL combinations can also be greatly improved using DBF. DBF uses an asymmetry signal which is translated directly to focus values and is independent of any focus settings of the scanner. After accurately determining the best focus using DBF on only one SRDL combination, the focus setting can be applied to all other combinations and scanners will be matched. Instead of exposing a FEM for each SRDL combination, best focus only needs to be determined once. Experiments using five different machine/reticle combinations show that Bossung tops can be matched with significantly more accuracy compared to POR. Experiments also show a linear relation between energy and shift in Bossung top; both DBF and CD are sensitive to energy variation. When correcting for energy differences, the Bossung top scanner-to-scanner matching accuracy can be improved further. A method using DBF for scanner best focus matching saves up to 10 hours of CD-SEM and manpower setup time per SRDL combination. When a scanner needs to be requalified, the same DBF focus setup method can be used, reducing the scanner downtime.
Reducing overlay error via an accurate APC feedback system is one of the main challenges in high volume production of the current and future nodes in the semiconductor industry. The overlay feedback system directly affects the number of dies meeting overlay specification and the number of layers requiring dedicated exposure tools through the fabrication flow. Increasing the former number and reducing the latter number is beneficial for the overall efficiency and yield of the fabrication process. An overlay feedback system requires accurate determination of the overlay error, or fingerprint, on exposed wafers in order to determine corrections to be automatically and dynamically applied to the exposure of future wafers. Since current and future nodes require correction per exposure (CPE), the resolution of the overlay fingerprint must be high enough to accommodate CPE in the overlay feedback system, or overlay control module (OCM). Determining a high resolution fingerprint from measured data requires extremely dense overlay sampling that takes a significant amount of measurement time. For static corrections this is acceptable, but in an automated dynamic correction system this method creates extreme bottlenecks for the throughput of said system as new lots have to wait until the previous lot is measured. One solution is using a less dense overlay sampling scheme and employing computationally up-sampled data to a dense fingerprint. That method uses a global fingerprint model over the entire wafer; measured localized overlay errors are therefore not always represented in its up-sampled output. This paper will discuss a hybrid system shown in Fig. 1 that combines a computationally up-sampled fingerprint with the measured data to more accurately capture the actual fingerprint, including local overlay errors. Such a hybrid system is shown to result in reduced modelled residuals while determining the fingerprint, and better on-product overlay performance.