**Publications**(38)

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^{9}op / s • W, which corresponds to the best technical solutions. In the work we are shown, that after sorting or comparative analysis of signals by levels of selected window of image, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We are shown that using this approach and the method of processing the current window signals significantly expands the set of operations and functions for filtering images, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined the set of executed command functions by such a processor based on the sorting node, show how it can be used to separate the rank from the array of signals and analyze the new approach for the programmable selection of the required rank or the difference between the signal ranks. The use of difference-rank decomposition allows to significantly expanding the transformations range, performed over the signals of the current fragment of the processed image. We determined set of basic possible executable instruction-functions by processors based on such a proposed method, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable choice of its function or set of functions, including the choice of the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that when using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

^{9}op / s•W, which corresponds to the best technical solutions. In the work we are shown, that after sorting or comparative analysis of signals by levels of selected window of image, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We are shown that using this approach and the method of processing the current window signals significantly expands the set of operations and functions for filtering images, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined set of basic possible executable instruction-functions by processors based on such a proposed method, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable choice of its function or set of functions, including the choice of the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that when using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

^{10}– 10

^{12}connections per second!) And the ability to process, store and associatively recognize highly correlated images. Next, we show that with minor modifications, such MP NN AAM can be successfully used for highperformance parallel clustering processing of images. We show simulation results of using these modifications for clustering and learning models and algorithms for cluster analysis of specific images and divide them into categories of the array. Show example of a cluster division of 32 images (40x32 pixels) letters and graphics for 12 clusters with simultaneous formation of the output-weighted space allocated images for each cluster. We discuss algorithms for learning and self-learning in such structures and their comparative evaluations based on Mathcad simulations are made. It is shown that, unlike the traditional Kohonen self-organizing maps, time of learning in the proposed structures of multi-port neuronet classifier/clusterizer (MP NN C) on the basis of equivalency paradigm, due to their multi-port, decreases by orders and can be, in some cases, just a few epochs. Estimates show that in the test clustering of 32 1280- element images into 12 groups, the formation of neural connections of the matrix with dimension of 128x120 elements occurs to tens of iterative steps (some epochs), and for a set of learning patterns consisting of 32 such images, and at time of processing of 1-10 microseconds, the total learning time does not exceed a few milliseconds. We offer criteria for the quality evaluation of patterns clustering with such MP NN AAM.

^{n}. Such simple structure of M SP ADC CM with low power consumption ≤3÷5mWand supply voltage (3-7)V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40 MHz, and can be increased up to 10 times) and accuracy (Δ

_{quantization}=156,25nA for I

_{max}=10μA ) characteristics are show. The range of optical signals, taking into account sensitivity of modern photo-detectors, can be 20-200 μW. Each channel of ADC, to reach the general power 50-100

_{μ}W for low power consumption, can consist of only one such ABC and analog memory. To implement such serial ADC no more than 40 CMOS transistors are needed. The M SP ADC CM opens new prospects for realization linear and matrix (with picture operands) micro photo-electronic structures which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers, and so forth.

*n*= n

_{e}- n

_{0}= - 0.35 at 550nm. The thin form factor and the ability to coat on a variety of substrates give coatable retarders a great degree of design flexibility and advantages in LCD related applications. LCD applications of TBF retarders are also discussed.

_{off}=1 15V, I

_{max}=50μA 30mA, I

_{off}=0.1 10nA. The advantage of such triggers is law energy consumption in the mode of logic levels storage (from units up to tenths of nanowatts at V=5V) and voltage of logic levels practically does not differ from potentials of the earth and supply (Δ≈10μV) such devices enable to be commutated with frequencies up to 360 MHz if the duration of optic pulses t=0.8ns and power 100mW (using photodiodes having responsivity 0.5A/W). That corresponds to the switching energy of 80pJ, average consumption power from supply circuits of 58mW. The decrease of switching frequency at the expense of increase of porosity of supplied pulses and usage of photoreceivers with high conversion efficiency of A/W allows to decrease energy consumption of trigger. Thus, if commutation frequency is 100kHz and duration of optic pulses is 320ns, power - 80μW, that corresponds to switching energy of 26pJ, and usage of photopreceivers having responsivity of 2.5 A/W, the consumed average power of considered optoelectronic trigger from supply circuit is 9μW. That permits to carry out their integration with the number of elements in a matrix is 32×32 and more. We consider simulation results of such optoelectronic triggers based on λ-devices with different circuits, principles of optical and electronic control and show advantages of such optoelectronic triggers and their multifunctionality.

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