<bold>Background:</bold> To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These additional degrees of freedom offer better leveling performance, but users hesitate to spend the tool time, wafers, and engineering hours necessary to find and maintain the optimal settings experimentally.</p><p>
<bold>Aim:</bold> In order to fully explore the potential of advanced leveling controls, an automated, fast simulation method should be introduced.</p><p>
<bold>Approach:</bold> Alternative set-point curves and resulting focus residuals are simulated from existing wafer height maps. Optimizations are carried out to obtain the best edge exclusion settings for several dynamic random access memory and NAND flash memory products, across different layers and exposure tools. The simulated focus errors are compared to the POR settings and verified with electrical results.</p><p>
<bold>Results:</bold> An efficient optimization algorithm was demonstrated and significant leveling improvements found for a number of use cases. The resulting settings vary substantially between different products, layers, and exposure tools. The impact of the improved leveling performance is verified using electrical data.</p><p>
<bold>Conclusions:</bold> The speed of the presented method proves crucial to help lithographers dial in and maintain numerous settings at optimal values across a typical production line.</p>
There are different approaches for alignment sampling optimization. In order to determine, which approach is optimal, OPAL run-to-run simulations<sup>1</sup> must be executed using the result of the different sampling optimization. This means that there is a two-step approach: first, an iterative sampling optimization algorithm that results in optimal overlay modeling. Then, a run-to-run simulation is done to verify the impact on the overlay performance.<p> </p> In this study, we investigate on the behavior of four different approaches to alignment sampling optimization on four different layers and analyze which approach is most suitable for which layer.
To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These can be explored fully with minimum experimental effort by simulating alternative set-point curves (<i>z; R<sub>x</sub>; R<sub>y</sub></i>) and resulting MA and MSD focus residuals from existing full wafer height maps. In this paper, optimizations are carried out to obtain the best focus edge clearance settings for several DRAM and NAND products, across different layers and exposure tools. The simulated die-fine focus errors are compared to the POR settings and verified with electrical results. Differences across products, layers, and exposure tools are discussed.