Dr. Alexander Starikov
at I&I Consulting
SPIE Involvement:
Conference Program Committee | Editorial Board Member: Journal of Micro/Nanolithography, MEMS, and MOEMS | Editorial Board Member: Journal of Micro/Nanopatterning, Materials, and Metrology | Author | Editor | Instructor
Area of Expertise:
microlithography, patterning , dimensional metrology, alignment, overlay , metrology, design, process integration , OPC, IC Design Rules, DR validation , process development, improvement, control , efficient development and manufacture
Profile Summary

Interests: Technologies, products, and applications for efficient manufacture of thin film electronic devices, integrated optics and similar structures.

Managed Intel’s first Proteus OPC technology transfer to shrink. Executed model based design validation and process margin improvements, meeting yield objectives on the 1st lot out. Enabled accelerated new technology qualification and conversion to shrink of all LOGIC products.

Investigated manufacturability of optical resolution enhancements for applications in microlithography. Invented and implemented effective 2-D OPC using optimal e-test based serif design, automated full-chip insertion and design validation. Extended lithography process window and yield from k1=1.0 to 0.5. Spearheaded industry-wide lithography extensions with OPC enabled by CAD/EDA, mask making, inspection and dimensional metrology.

Developed alignment and overlay metrology at IBM. Troubleshot alignment issues with Censor and GCA, collaborated on alignment in step-and-scan JD with Perkin-Elmer. Characterized and modeled error mechanisms, established effective performance metrics (now standard), enabled and drove improvements, influenced equipment vendors, consortia and industry. According to VLSI Research, “forever changed overlay measurement requirements”.

Lead metrology-process integration in IBM-Siemens-Toshiba DRAM partnerships resulting in elimination of a widely anticipated overlay roadblock at 250nm/256Mb. Co-developed SEM based in-die overlay metrology for FE and AlCu/W Damascene BE. Invented effective dose and focus monitors for applications with optical metrology tools.

Managed Ultratech Alignment/Metrology Engineering, supported applications, collaborated with strategic customers. Delivered wafer global and fine alignment in narrow scribes. Developed stepper self-metrology and accelerated reduction of alignment and registration error, improved tool stability and matching. Enabled new market penetration and new system sales
Publications (11)

SPIE Journal Paper | 17 June 2019
JM3 Vol. 18 Issue 02
KEYWORDS: Overlay metrology, Scanning electron microscopy, Metrology, Optical lithography, Integrated circuits, Edge detection, Critical dimension metrology, Control systems, Distance measurement, Data analysis

SPIE Journal Paper | 30 June 2016
JM3 Vol. 15 Issue 02
KEYWORDS: Metrology, Overlay metrology, Control systems, Optical lithography, Process control, Integrated circuits, Lithography, Critical dimension metrology, Optical proximity correction, Image processing

SPIE Journal Paper | 26 June 2015
JM3 Vol. 14 Issue 02
KEYWORDS: Process control, Metrology, Critical dimension metrology, Electron beam lithography, Optical lithography, Optical proximity correction, Scanning electron microscopy, Calibration, Device simulation, Directed self assembly

SPIE Journal Paper | 25 March 2014
JM3 Vol. 13 Issue 01
KEYWORDS: Metrology, Inspection, 3D metrology, Process control, Integrated circuits, 3D modeling, Manufacturing, Roads, Standards development, Control systems

Proceedings Article | 24 March 2008 Paper
Proc. SPIE. 6922, Metrology, Inspection, and Process Control for Microlithography XXII
KEYWORDS: Metrology, Critical dimension metrology, Semiconducting wafers, Manufacturing, Scanning electron microscopy, Image processing, Etching, Lithography, Optical alignment, Process control

Showing 5 of 11 publications
Proceedings Volume Editor (7)

Showing 5 of 7 publications
Conference Committee Involvement (22)
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV
22 February 2021 | Online Only, California, United States
Metrology, Inspection, and Process Control for Microlithography XXXIV
24 February 2020 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXXIII
25 February 2019 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXXII
26 February 2018 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXXI
27 February 2017 | San Jose, California, United States
Showing 5 of 22 Conference Committees
Course Instructor
SC1158: Metrology of Image Placement
This course explains basic principles of metrology of image placement for applications to registration, alignment, and overlay in IC manufacture. Starting with IC Design Rules, and device pattern size and placement as their basis, this course outlines a systematic approach to dimensional metrology. Device pattern variation in mask-making, lithography imaging, image recoding, and image transfer, and down-stream wafer processing, are discussed leading to requirements of dimension metrology and control. Expectations in metrology of image placement are examined in the context of semiconductor design and manufacturing paradigm: device invariance in transformations of symmetry and translation, universal coordinate system, and absolute scale being the foundation of IC design. These attributes, built into IC design, are maintained in production by the use of isoplanatic lithography systems, dimensionally stable masks, stages, and wafers, control of coordinate systems and, of course, spatially uniform semiconductor processing. The key performance metrics for metrology of image placement are defined, and illustrated, in applications to improving robustness and accuracy in production environment. Systematic quantitative validation of those expectations for metrology systems and targets used, with complementary validation means and measurement technology, establish the foundation for certifiably accurate metrology of image placement and comprehensive control of overlay in IC manufacture.
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