For capacity reasons, it is interesting for us to have the flexibility of switching lithography processes between DUV and I-line steppers. The following discussion concentrates on high energy tilted implants of CMOS technology, critical enough to be worth running on the more expensive DUV equipment. As far as the differences are understood at the level of the printing, as well as the dissimilarities during the following implantation steps, it is possible using the same reticle and with minor target adjustments, to switch between the 2 tools/processes when required. This paper investigates the most important differences between the functionality of a same implant layer making use of the two wavelengths. Taken as high energy implant mask for several successive ion implantations, the resist film considered here is 1.6 pm thick. The taper profiles of I-line and DUV resist are shown after development, and after the successive implantation steps. Both wavelengths provide straight profiles after development, with one main difference: a slight footing for the I-line resist. This can be very well seen on the corresponding top down pictures revealing more tapers for the I-line process than for DUV. The first implantation step following development influences the profiles the most. In fact the profile of the DUV resist changes considerably while the one with I-line resist remains unchanged. That can be explained by the fact that the aliphatic structure of DUV photoresist is less resistant to degradation by ion bombardment as compared to the highly aromatic chemical structure of I-line photoresist. The subsequent implant steps of lower energy do not further influence the tapers, not even in the case of the I-line film. Therefore the biggest shrinkage occurs during the first implantation and all the next ion sequences will see this first deformation without changing it. Finally, simulation show that, an adjustment of the reticle OPC by adding serifs can be beneficial to the I-line layer to diminish corner rounding where the footingkapering can be worse.
As chip dimensions decrease, I-line processes remain of interest for most uncritical layers: they provide the needed
performance at a low cost and high throughput. However the critical dimensions (CD) and overlay requirements for
the newest technologies are much tighter than they used to be, reducing significantly the process windows. Sources
of variations of CD range and CD mean should be well known and the process window set up so as to minimize the
sensitivity to small variations.
For lower resist thickness, although using partially dyed I-line resist, one may have to deal with huge swing effects.
Resist thickness and stack variations are then the main contributors to the high CD distribution This article focuses
on CD instabilities caused by resist thickness fluctuations in the case where a stack layer is subject to variations.
The influence of resist thickness variations is first considered, pointing out the importance of thickness control
methods. The real resist thickness repartition on stacked wafers depends not only on global coating uniformity but
also on local topography. Some examples of resist repartition and its impact on CD-uniformity are provided.
The added contributions of resist and stack to a global swing effect are then discussed on the basis of experimental
data. Significant differences of swing behavior are experimentally observed between critical chip structures and the
usually monitored PCI kerf structure. A simulation illustrates the effect of the local stack thickness and resist
thickness and to better understand those differences, together with cross section thickness measurements.
The choice of an appropriate CD control structure is finally dealt with.
As chip dimensions decrease, I-line steppers can still provide very good performance for uncritical layers at low cost and high throughput. However, while older technologies are relatively insensitive to tool and process variations, process control of advanced technologies on I-line becomes critical. In this paper, we will concentrate on critical dimension variations of I-line lithography and provide some examples. The topics considered here primarily cover variations in CD range and CD mean that can be detected in SPC charts. We also discuss the benefits and drawbacks of measurements performed in the kerf rather than in the chip, in relation with the above CD control investigation. Finally we discuss how sampling should be effectively related to the process stability (Cpk values).
Implantation layers may require smaller resist thickness as chip dimensions decrease. When reducing the thickness below 800 nm, while keeping all other track and exposure settings the same, standing waves in positive and negative I-line resists become more prominent. Bottom antireflective coating helps reducing the amplitude of the waves, but additional efforst, like BARC open RIE steps, or more coater units on the track, will increase the cost of ownership significantly. One may also consider changing the bake settings, which play a critical role in the formation of standing waves. The standard settings used for mid UV resists are 90 deg post apply bake (PAB) and 110 deg post exposure bake (PEB). Although resist suppliers recommend staying within this temperature range, we have used settings outside the range, as part of testing for possible profile ameliorations. Optimized settings for both tones were achieved with a different combination of the two bakes. The overall performances of the tested samples with optimized settings were satisfying in terms of CD range, stability and process window.
Tapered resist profiles have been found to cause a deterimental effect on the overlay measurement capability, affecting lithography processes which utilize thick implant resist. Particularly, for resist thicknesses greater than 1.5 μm, the systematical contribution to the overlay error becomes predominant. In CMOS manufacturing, these resist types are being used mainly for high energy well implants. As design rules progressively shrink, the overlay requirements are getting tighter, such that the limits of the process capability are reached. Since the resist thickness cannot be reduced due to the requirements of the implant process, it becomes inevitable to reduce the systematical overlay error for the litho process involving thick resists. The following analysis concentrates on the tapers of overlay marks printed on thick i-line positive resists. Conventionally, overlay between two litho layers is measured from box in box marks with respect to a reference layer where the statistical shift between the boxes is expected to provide the biggest source of residuals. We observed however that an even bigger error could be introduced by an unevenness of the i-line resist tapers, adding asymmetrical chip magnification. The inclination of these tapers depends on the proximity and surface of the surrounding features and stack variations. We show that by adjusting soft and hard bake temperatures and times, tapers can be significantly reduced and thereby the overlay performance was greatly improved.