Microfluidic devices are currently being utilized in many types of BioMEMS and medical applications. In
these systems, the interaction between the surface and the biological specimen depends critically on surface properties.
The surface roughness and chemistry as well as the surface area to which the biomolecules or cells are exposed affect
this interaction. Modification of the surface of microfluidic channels can improve the operation of the device by
influencing the behavior of the biological specimens that are flowing through it. SU-8 is an epoxy-based, negative
photoresist that has been previously used to create covered channels. Once cured, it is both chemically and thermally
stable. It is also optically transparent above 360 nm, which allows optical measurements, including fluorescence
imaging, to be taken inside the channel. SU-8 microchannels have been fabricated with a porous layer on the sidewalls
by the photo-lithographic process, which is reproducible with precisely controlled channel dimensions. In order to attain
these porous sidewalls, no additional fabrication steps are required outside the standard photo-lithographic process. The
porosity of the sidewalls is a result of incomplete cross-linking of the polymer. The obtained porous surfaces can be
specially treated to provide conditions preferable for biological interactions. The porous layer increases the internal
surface area available on the sidewalls, which make these microfluidic channels preferable for biological applications.
This paper describes the details of the fabrication process and the experiments that verify the benefit of using SU-8
microchannels with porous sidewalls.
Optical interferometry is a well established technique for high resolution displacement measurements. It is commonly used in the semiconductor industry as a sub-system of manufacturing and metrology tools. As the industry progresses, the tools continue to evolve, requiring the concomitant reduction of size and cost in sensors. Existing interferometric systems are bulky and therefore difficult to incorporate in equipment. Efforts are ongoing to miniaturize these systems but with optical components (beam splitters, detectors and lasers) still in the millimeter range, it is difficult to realize ultra compact systems. Thus, it is imperative to focus on development of micron scale components that would provide the necessary high spatial resolution in a compact format.
The focus of this paper is on the development of a micron size optical component that combines multiple optical elements and can be integrated with VCSELs at the wafer level to yield a compact, low cost interferometric system. The design and development of this component containing the beam splitter and reference mirror will be presented including the investigation of suitable polymeric materials with desirable optical properties and appropriate fabrication techniques. Preliminary optical measurements of the integrated system will also be demonstrated. This approach has the potential to impact the next generation of micron scale interferometers as precise position/proximity sensors.
We describe two types of active optical devices developed for
use as free-space optical interconnects FSOIs for chip-to-chip communications.
The design of both types of devices—membrane and freestanding
structures—includes both optical and mechanical components.
The optical component contains porous silicon PSi with customized
optical properties fabricated by electrochemical etching of silicon. The
mechanical part of the devices is composed of metal/nitride bimorph
thermal actuators. The membrane devices form concave mirrors when
actuated, and can be used to focus the incoming optical signals and
correct any optical misalignment within the input/output I/O fabric. The
freestanding devices have out-of-plane optical components, whose tilting
angle is controlled by the current applied to the actuator. These devices
can function as either reflectors or tunable optical filters. By incorporating
the developed PSi diffractive optical element DOE into the freestanding
structure, another type of freestanding device is realized for beamsplitting
applications. Details of the fabrication, testing, and integration of
these PSi-based devices are presented.
Porous silicon (PSi) is a promising material for the creation of optical components for chip-to-chip interconnects because
of its unique optical properties, flexible fabrication methods and integration with conventional CMOS material sets. In
this paper, we present a novel active optical filter made of PSi to select desired optical wavelengths. The tunable
membrane type optical filter is based on a Fabry-Perot interferometer employing two Bragg reflectors separated by an
adjustable air gap, which can be thermally controlled. The Bragg reflectors contain alternating layers of high and low
porosities. These layers were created by electrochemical etching of p+ type silicon wafers by varying the applied current
during etching process. Micro bimorph actuators are designed to control the movement of the top DBR mirror, which
changes the cavity thickness. By varying the applied current, the proposed filter can tune the transmitted wavelength of
the optical signal. Various geometrical shapes and sizes ranging from 100μm to 1mm of the active filtering region have
been realized for specific applications. The MOEMS technology-based device fabrication is fully compatible with the
existing IC mass fabrication processes, and can be integrated with a variety of active and passive optical components to
realize inter-chip or intra-chip communication at the system level at a relatively low cost.
With the continued miniaturization and sophistication of current generations of semiconductor devices, it is the
limitations of data transfer rates that are beginning to impact system performance. Although conventional pathways
continue progressing, researchers are moving toward optical interconnects as a potential solution. Optical
interconnection is a promising way to replace existing global or chip-to-chip interconnects in future integrated
circuits. In contrast to existing metallic wiring, optical interconnects exhibit smaller distance-related loss or
distortion of the signal, no deleterious fringing effects and no heat dissipation in the interconnect itself.
Pioneering interconnect schemes are currently being developed using both planar waveguides and fibers to distribute
optical signals around printed circuit boards. However, researchers are now attempting to incorporate novel, freespace
optical interconnects, which will boost data transfer rates by a factor of a thousand. These systems consist of
a number of components including vertical cavity surface emitting lasers (VCSELs), lenses, diffractive optical
elements and detectors. Integration of single components into sub-systems will help to minimize the optical system
footprint for both on-chip and chip-to-chip interconnects.
This paper will present the development of both independent and integrated with VCSELs,static diffractive optical
element (DOEs) made of SU8 and prove the feasibility of such an approach. SU8 is a negative tone photoresist,
conventionally used for high aspect ratio MEMS-based structures. Recent developments in thin film SU8 along
with its low absorption at long wavelengths makes it a suitable material for optical applications. By developing a
low cost lithography based process, SU-8 DOEs can be efficiently integrated directly on laser sources with minimal
effect to VCSEL performance. This approach could have a significant impact on the creation of next generation
optical I/O fabrics.
Porous silicon (PSi) is an attractive material for fabrication of multilayer optical devices such as Bragg
reflectors, Fabry-Perot resonators and other novel (optical) components. Such devices are characterized by a
periodic modulation of the refractive indices in alternating layers and can be classified as 1D photonic crystals. 2D
photonic bandgap structures can be also obtained using a variation of applied potential on the back side of the
sample during electrochemical formation of the multilayers. This technique allows a fabrication of spatially
distributed filters on the millimeter size scale. In this paper, a new method is presented which uses a front side
protective mask for the creation of 2D photonic bandgap structures on the micron scale. The devices obtained by this
technique can be used for the creation of spatially distributed filters. The front side protective mask controls lateral
undercut in multiple ways depending on the mask material. By varying the design and material of the protective
mask, PSi interference filters with desired optical parameters across a field of view can be realized.
In this paper, a novel, simple method to produce 2D periodic multilayer structures is described. In
particular, the focus is on the changes in the photonic crystal cavities when various mask materials are used. In
addition, a new type of active optical components for a chip-to chip interconnection based on the combination of our
method and MEMS technology is presented.
We focus on the development and fabrication of SU8TM-based microchannel networks, which can be integrated into microdevices for fast drug delivery and cell transport on chips. Instead of using sacrificial materials or wafer bonding, a new simplified fabrication method is developed. Single- and double-layered SU8TM channels on silicon substrates are successfully achieved by using this new method, as well as integration of these SU8 channels with microelectrode arrays. A series of cell transport experiments is also successfully performed on these devices. This new fabrication approach and the resulting cell transport experiments are discussed in detail.
To assist the growth of the telecommunication sector, new types of optical components such as those based on optical interference filter technology are critical. Existing technologies based on thin-film processing for production of optical communications filters have rapidly advanced. Although the Fabry-Perot bandpass filters made by deposition of alternate layers with high- and low- refractive index have a broad rejection band and a narrow passband, this technique does not allow for the control of filter parameters such as specification and adjustment of the transmitted wavelength at any place across the surface of the filter. The new approach discussed in the paper is directed toward the anodization of silicon to fabricate not only multilayer optical filters with a uniform passband across the field of view but also specially designed passbands at any single point in the field of view of the optical system. In particular, the realization and characterization of spatially distributed filters made of porous silicon are presented. These filters are able to select various passbands in the visible and IR regions. The filters were fabricated on p<sup>+</sup> and p - type doped substrates. By varying the electrode configuration on the backside of wafer and the applied potential during electrochemical etching, the desired spatially distributed filter can be formed. The impact of wafer resistivity on filter parameters is discussed.
The pressure for reduction in cost and development time in new product, together with the need to pack more functions into smaller volumes in silicon chips has been fueling the system-on-chip (SOC) development. However, the current SOC technologies available essentially involve merging of chips fabricated with standard CMOS technology. These SOC technologies provide an integration solution with compatible fabrication processes that require little changes in process integration. There is no standard cost-effective solution to make 3D MEMS and optoelectronic devices together with CMOS on the same chip without compromising material compatibility, process complexity and system performance. One solution is to fabricate MEMS and CMOS components on separate wafer substrates and then stack them together with well isolated interconnected vias. In order to demonstrate this wafer-level 3D integration technology, a novel wafer-level bonding technology is being developed. This paper reports a detailed study of 3D MEMS (Micro Electro-Mechanical Systems) integration through multi-wafer anodic and polymeric wafer bonding. Different from previously reported wafer bonding studies, this study focuses on the optimization of the bonding process to improve the bonding quality.
This paper focuses on the development of two MEMS-based devices for lab-on-a-chip bio-applications. The first device is designed to facilitate cell secretion studies by enabling parallel electrochemical detection with millisecond resolution. Initial prototypes of micro-arrays have been fabricated with Cr/Au microelectrodes on various substrates such as polyimide, SU-8 and SiO<sub>2</sub>. An FT cell-line (bullfrog fibroblast, American Tissue Culture Collection) has been successfully established and cultured directly on these prototype micro-arrays. It is well known that the FT cells can uptake hormones or other macromolecules from the culture media through a non-specific uptake mechanism which is still under investigation. After culturing on micro-arrays, FT cells were loaded with norepinephrine of various concentrations by incubation in the culture media supplied with norepinephrines. Rapid elevation of intracellular Ca<sup>2+</sup> levels triggers the exocytosis of norepinephrine which then can be detected by the Cr/Au electrodes. Microfabrication of these prototype micro-arrays as well as cell culture and electrochemical detection results will be presented in this paper. The second device is designed for 3-dimensional transportation of living cells on chips. Initial prototypes of micro-arrays were fabricated with SU-8 buried channels on a silicon substrate. Both single-layered and double-layered SU-8 buried channels have been realized to enable 2D and 3D cell transportation. Stained solutions were used to visualize fluid transport through the channel networks. Following this, living FT cells in solution were successfully transported through single-layered SU-8 channels. Testing of 3D transportation of living FT cells is underway. Microfabrication of these prototype micro-arrays and living cell transportation on chips will also be presented in this paper.
Wafer bonding has attracted significant attention in applications that require integration of Micro-Electro-Mechanical Systems (MEMS) with Integrated Circuits (IC). The integration of monolithic MEMS and electronic devices is difficult because of issues such as material compatibility, process compliance and thermal budget. It is important to establish a wafer bonding process which provides long-term protection for the MEMS devices yet does not affect their performance. The attentions for such integration are at the die level and wafer level. Recently, the trend is toward wafer-level integration as a cost effective solution to combine sensing, logic, actuation and communications on a single platform. This paper describes the development of low temperature bonding techniques for post-CMOS MEMS integration in system-on-chip (SOC) applications. The bonding methods discussed in this paper involve Benzocyclobutene polymer (BCB) as glue layer to joint two 200 mm wafers together. The bonding temperature is lower than 400°C. Four-point bending and stud-pull methods were used to investigate the mechanical properties of the bonding interfaces. These methods can provide critical information such as adhesion energy and bonding strength of the bonded interfaces. Initial test results at room temperature showed that the BCB bond stayed intact up to an average stress of 50 MPa. It was observed that the BCB bond strength decreased with increasing temperatures and the energy release rate decreased with decreasing BCB thickness.