An important step in today's Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). In
model based OPC, masks are systematically modified to compensate for the non-ideal optical and process effects
of optical lithography system. The polygons in the layout are fragmented, and simulations are performed to
determine the image intensity pattern on the wafer. Then the mask is perturbed by moving the fragments to
match the desired wafer pattern. This iterative process continues until the pattern on the wafer matches the
desired one. Although OPC increases the fidelity of pattern transfer to the wafer, it is quite CPU intensive; OPC
for modern IC designs can take days to complete on computer clusters with thousands of CPU. In this paper,
techniques from statistical machine learning are used to predict the fragment movements. The goal is to reduce
the number of iterations required in model based OPC by using a fast and efficient solution as the initial guess to
model based OPC. To determine the best model, we train and evaluate several principal component regression
models based on prediction error. Experimental results show that fragment movement predictions via regression
model significantly decrease the number of iterations required in model based OPC.
An important step in today's Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. To alleviate the growing volume of layout data, a new layout data format, Open Artwork System Interchange Standard (OASIS), was introduced in 2001 by SEMI's Data Path Task Force. Even though OASIS results in a more efficient representation than the previous industry standard format GDSII, there is still room for improvement by applying data compression techniques. In this paper, we propose two such techniques for compressing layout data, including OPC layout, while remaining complaint with existing industry standard formats such as OASIS and GDSII. Such compliance ensures that the resulting compressed files can be viewed, edited, and manipulated by industry standard CAD viewing and editing tools without the need for a decoder. Our approach is to eliminate redundancies in the representation of the geometrical data by finding repeating groups of geometries between multiple cells and within a cell. We refer to the former as "inter-cell sub-cell detection (InterSCD)" and latter as "intra-cell sub-cell detection (IntraSCD)". We show both problems to be NP hard, and propose two sets of heuristics to solve them. For OPC layout data, we also propose a fast compression method based on IntraSCD which utilizes the hierarchical information in the pre-OPC layout data. We show that the IntraSCD approach can also be effective in reconstructing hierarchy from flattened layout data. We demonstrate the results of our proposed algorithms on actual IC layouts for 90nm, 130nm, and 180nm feature size circuit designs.