Reflective electron-beam lithography (REBL) employs a novel device to impress pattern information on an electron
beam. This device, the digital pattern generator (DPG), is an array of small electron reflectors, in which the reflectance
of each mirror is controlled by underlying CMOS circuitry. When illuminated by a beam of low-energy electrons, the
DPG is effectively a programmable electron-luminous image source. By switching the mirror drive circuits
appropriately, the DPG can ‘scroll’ the image of an integrated circuit pattern across its surface; and the moving electron
image, suitably demagnified, can be used to expose the resist-coated surface of a wafer or mask. This concept was first
realized in a device suitable for 45 nm lithography demonstrations. A next-generation device has been designed and is
presently nearing completion. The new version includes several advances intended to make it more suitable for
application in commercial lithography systems. We will discuss the innovations and compromises in the design of this
next-generation device. For application in commercially-practical maskless lithography at upcoming device nodes, still
more advances will be needed. Some of the directions in which this technology can be extended will be described.
KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL), targeted as a production worthy multiple electron beam tool for next generation high volume lithography. The Digital Pattern Generator (DPG) integrated with CMOS and MEMS lenslets is a critical part of REBL. Previously, KLA-Tencor reported on progress towards a REBL tool for maskless lithography below the 10 nm technology node. However, the MEMS lenslet structure suffered from charging up during writing, requiring the usage of a charge drain coating. Since then, the TSMC multiple e-beam team and the KLA-Tencor REBL team have worked together to further develop the DPG for direct write lithography. In this paper, we introduce a hollow-structure MEMS lenslet array that inherently prevents charging during writing, and preliminary verification results are also presented.
The digital pattern generator (DPG) is a complex electron-optical MEMS that pixelates the electron beam in the reflective electron beam lithography (REBL) e-beam column. It potentially enables massively parallel printing, which could make REBL competitive with optical lithography. The development of the REBL DPG, from the CMOS architecture, through the lenslet modeling and design, to the fabrication of the MEMS device, is described in detail. The imaging and printing results are also shown, which validate the pentode lenslet concept and the fabrication process.
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half
pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL)
technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing
system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL
system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable
of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons
are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The
DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed.
Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below
the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the
REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled
DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of
over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron
beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern
scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in
both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying
the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design
improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current
chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be
Maskless electron beam lithography has the potential to extend semiconductor manufacturing to the sub-10 nm technology node. KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL) for high-volume 10 nm logic (16 nm HP). This paper reviews progress in the development of the REBL system towards its goal of 100 wph throughput for High Volume Lithography (HVL) at the 2X and 1X nm nodes. In this paper we introduce the Digital Pattern Generator (DPG) with integrated CMOS and MEMs lenslets that was manufactured at TSMC and IMEC. For REBL, the DPG is integrated to KLA-Tencor pattern generating software that can be programmed to produce complex, gray-scaled lithography patterns. Additionally, we show printing results for a range of interesting lithography patterns using Time Domain Imaging (TDI).<p> </p>Previously, KLA-Tencor reported on the development of a Reflective Electron Beam Lithography (REBL) tool for maskless lithography at and below the 22 nm technology node<sup>1</sup>. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam direct write lithography has been too slow for most lithography applications. Ebeam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVL.
REBL (Reflective Electron Beam Lithography) is a novel concept for high speed maskless projection electron beam
lithography. Originally targeting 45 nm HP (half pitch) under a DARPA funded contract, we are now working on
optimizing the optics and architecture for the commercial silicon integrated circuit fabrication market at the equivalent of
16 nm HP. The shift to smaller features requires innovation in most major subsystems of the tool, including optics, stage,
and metrology. We also require better simulation and understanding of the exposure process.
In order to meet blur requirements for 16 nm lithography, we are both shrinking the pixel size and reducing the beam
current. Throughput will be maintained by increasing the number of columns as well as other design optimizations. In
consequence, the maximum stage speed required to meet wafer throughput targets at 16 nm will be much less than
originally planned for at 45 nm. As a result, we are changing the stage architecture from a rotary design to a linear
design that can still meet the throughput requirements but with more conventional technology that entails less technical
risk. The linear concept also allows for simplifications in the datapath, primarily from being able to reuse pattern data
across dies and columns. Finally, we are now able to demonstrate working dynamic pattern generator (DPG) chips,
CMOS chips with microfabricated lenslets on top to prevent crosstalk between pixels.
REBL (Reflective Electron Beam Lithography) is a program for the development of a novel approach for highthroughput
maskless lithography. The program at KLA-Tencor is funded under the DARPA Maskless Nanowriter
Program. A DPG (digital pattern generator) chip containing over 1 million reflective pixels that can be individually
turned on or off is used to project an electron beam pattern onto the wafer. The DARPA program is targeting 5 to 7
wafers per hour at the 45 nm node, and this paper will describe improvements to both increase the throughput as
well as extend the system to the 2x nm node and beyond.
This paper focuses on three specific areas of REBL technology. First, a new column design has been developed
based on a Wien filter to separate the illumination and projection beams. The new column design is much smaller,
and has better performance both in resolution and throughput than the first column which used a magnetic prism for
separation. This new column design is the first step leading to a multiple column system. Second, the rotary stage
latest results of a fully integrated DPG CMOS chip with lenslets will be reviewed. An array of over 1 million micro
lenses which is fabricated on top of the CMOS DPG chip has been developed. The microlens array eliminates
crosstalk between adjacent pixels, maximizes contrast between on and off states, and provides matching of the NA
between the DPG reflector and the projection optics.
REBL (Reflective Electron Beam Lithography) is being developed for high throughput electron beam direct write
maskless lithography. The system is specifically targeting 5 to 7 wafer levels per hour throughput on average at the
45 nm node, with extendibility to the 32 nm node and beyond. REBL incorporates a number of novel technologies
to generate and expose lithographic patterns at estimated throughputs considerably higher than electron beam
lithography has been able to achieve as yet. A patented reflective electron optic concept enables the unique
approach utilized for the Digital Pattern Generator (DPG). The DPG is a CMOS ASIC chip with an array of small,
independently controllable cells or pixels, which act as an array of electron mirrors. In this way, the system is
capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely
high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the
writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The
exposure method utilized by the DPG was emulated on a Vistec VB-6 in order to validate the gray level exposure
method used in REBL. Results of these exposure tests are discussed.
The recently installed Sigma7100 laser pattern generator brings a new concept into photomask manufacturing. The spatial light modulator (SLM) technology enables 2D patterning using commercially available 248 nm lasers. This wavelength shift from the 413 nm wavelength of the Omega6000 scanning laser pattern generators facilitates the high resolution needed for 100 nm mask production. In addition, the partially coherence of the 2D patterning further enhances CD linearity and edge acuity. The rapidly increasing mask costs are partially attributed to increasing photomask writing times. These tend to increase as feature density increases with the roadmap, which is a challenge for any pattern generator with a limited number of writing beams. Instead, the SLM technology relies on the massive parallelism of one million micromirrors in combination with gray-scale control for fine addressing. A real-time FPGA-based data-rendering engine matches the speed. The result is pattern generation with high resolution at manageable mask writing times
Micronic is developing a massively parallel pattern generation system based on a micro-mechanical spatial light modulator (SLM). The electro-mechanical and optical properties of the micromirrors in the SLM can vary from one to another and over time. Therefore the response of each mirror must be calibrated, with accuracy sufficient to maintain CD uniformity requirements. We present a practical method for performing this calibration which greatly improves the micromirror grayscale uniformity and reduces CD error contribution from the SLM to less than 2nm.