Within the world of integrated circuit manufacturing there is a continuous effort to increase device density in order to improve speed, performance and costs. Current technology is driving a transition from devices that use a planar transistor to a more “3D” design, such as with nanowires or even vertically oriented transistors. The fabrication of nanowire devices demonstrates a good example of 3D etch challenges where both anisotropic and highly selective isotropic etch processes are needed. Alternating Si and SiGe layers are first etched vertically, then are later recessed selective to one another. There are a number of literature reports which have demonstrated the capability of recessing SiGe selective to Si, however the opposite is not as well established. The key challenges of this task are maximizing the selectivity to the SiGe layers as well as any other spacer and mask materials exposed on the wafer including SiO<sub>2</sub>, Si<sub>3</sub>N<sub>4</sub>, SiOCN and SiBCN. In this work, we present a study of isotropic etching for Si selective to SiGe in CF<sub>4</sub>/O<sub>2</sub>/N<sub>2</sub> and NF<sub>3</sub>/O<sub>2</sub>/N<sub>2</sub> based plasmas with selectivities higher than 50:1 achieved. Potential selectivity mechanisms are based on preferential oxidation of mixed SiGe layers opposed to Si, while formation of the NO molecule can result in excessive oxide layer removal from the Si surface.<sup>1,2</sup> A qualitative model is put forth to describe the resulting etch profiles using this chemistry. Supporting data regarding F:O ratio, temperature, and Si layer thickness dependency are shown in efforts to support the model. These results will provide essential insight as the industry decides which process solution is optimal for GAA devices.
Etch processes have always involved inherent process trade-offs related to fundamental plasma parameters to achieve planar patterning metrics related to damage, aspect ratio dependences and profile. Today, we are in a new era of “area selective etch.” Advanced patterning (SAXP, (LELE)n), logic, memory and interconnect applications beyond 3 nm involve, in one way or another, topographies that require etch “control” at every surface. Achieving profile specifications will require the ability to conjure isotropy control at will. Vehicles to achieving this include novel precursors and hybrid processes involving combinations of deposition and plasma etch as we know it. Ultimately, to differentiate surfaces comprising silicon, silicon oxides and nitrides, and organics require active modification at the first surface reactive monolayer to be able to differentiate them in each process step with respect to any surface normal on the wafer plane. This presentation will start with a review of today’s state-of-the-art means for atomic precision processing of surfaces. A simulation science perspective to process integration modeling introduces methods for surface chemistry control that lend themselves to achieving area selective etch. In the end, surface chemistry control is not a cure-all. Finally, a combination of plasma diagnostics and simulation will be needed to assist plasma process controls for scaling at 3 nm and beyond.
Interest in atomic layer etching (ALE) has surged recently because it offers several advantages over continuous or quasicontinuous plasma etching. These benefits include (1) independent control of ion energy, ion flux, and radical flux, (2) flux-independent etch rate that mitigates the iso-dense loading effects, and (3) ability to control the etch rate with atomic or nanoscale precision. In addition to these benefits, we demonstrate an area-selective etching for maskless lithography as a new frontier of ALE. In this paper, area-selective etching refers to the confinement of etching into the specific areas of the substrate. The concept of area-selective etching originated during our studies on quasi-ALE of silicon nitride which consists of sequential exposure of silicon nitride to hydrogen and fluorinated plasma. The findings of our studies reported in this paper suggest that it may be possible to confine the etching into specific areas of silicon nitride without using any mask by replacing conventional hydrogen plasma with a localized source of hydrogen ions.
Multi-layer patterning schemes involve the use of Silicon containing Anti-Reflective Coating (SiARC) films for their anti-reflective properties. Patterning transfer completion requires complete and selective removal of SiARC which is very difficult due to its high silicon content (>40%). Typically, SiARC removal is accomplished through a non-selective etch during the pattern transfer process using fluorine containing plasmas, or an ex-situ wet etch process using hydrofluoric acid is employed to remove the residual SiARC, post pattern transfer. Using a non-selective etch may result in profile distortion or wiggling, due to distortion of the underlying organic layer. The drawbacks of using wet etch process for SiARC removal are increased overall processing time and the need for additional equipment. Many applications may involve patterning of active structures in a poly-Si layer with an underlying oxide stopping layer. In such applications, SiARC removal selective to oxide using a wet process may prove futile. Removing SiARC selectively to SiO<sub>2</sub> using a dry etch process is also challenging, due to similarity in the nature of chemical bonds (Si – O) in the two materials. <p> </p>In this work, we present highly selective etching of SiARC, in a plasma driven by a surface wave radial line slot antenna. The first step in the process involves an in-situ modification of the SiARC layer in O2 plasma followed by selective etching in a NF<sub>3</sub>/H<sub>2</sub> plasma. Surface treatment in O<sub>2</sub> plasma resulted in enhanced etching of the SiARC layer. For the right processing conditions, in-situ NF<sub>3</sub>/H<sub>2</sub> dry etch process demonstrated selectivity values greater than 15:1 with respect to SiO<sub>2</sub>. The etching chemistry, however, was sensitive to NF<sub>3</sub>:H<sub>2</sub> gas ratio. For dilute NF<sub>3</sub> in H<sub>2</sub>, no SiARC etching was observed. Presumably, this is due to the deposition of ammonium fluorosilicate layer that occurs for dilute NF<sub>3</sub>/H<sub>2</sub> plasmas. Additionally, challenges involved in selective SiARC removal (selective to SiO2, organic and Si layers) post pattern transfer, in a multi-layer structure will be discussed.
Proc. SPIE. 10149, Advanced Etch Technology for Nanopatterning VI
KEYWORDS: Oxides, Optical lithography, Etching, Image processing, Interfaces, Ions, 3D modeling, Monte Carlo methods, Plasma etching, Chemical elements, Semiconducting wafers, Bromine, Process modeling, Plasma
Increasingly, advanced process nodes such as 7nm (N7) are fundamentally 3D and require stringent control of critical dimensions over high aspect ratio features. Process integration in these nodes requires a deep understanding of complex physical mechanisms to control critical dimensions from lithography through final etch. Polysilicon gate etch processes are critical steps in several device architectures for advanced nodes that rely on self-aligned patterning approaches to gate definition. These processes are required to meet several key metrics: (a) vertical etch profiles over high aspect ratios; (b) clean gate sidewalls free of etch process residue; (c) minimal erosion of liner oxide films protecting key architectural elements such as fins; and (e) residue free corners at gate interfaces with critical device elements. In this study, we explore how hybrid modeling approaches can be used to model a multi-step finFET polysilicon gate etch process. Initial parts of the patterning process through hardmask assembly are modeled using process emulation. Important aspects of gate definition are then modeled using a particle Monte Carlo (PMC) feature scale model that incorporates surface chemical reactions.<sup>1</sup> When necessary, species and energy flux inputs to the PMC model are derived from simulations of the etch chamber. The modeled polysilicon gate etch process consists of several steps including a hard mask breakthrough step (BT), main feature etch steps (ME), and over-etch steps (OE) that control gate profiles at the gate fin interface. An additional constraint on this etch flow is that fin spacer oxides are left intact after final profile tuning steps. A natural optimization required from these processes is to maximize vertical gate profiles while minimizing erosion of fin spacer films.<sup>2</sup>
EUV based patterning is one of the frontrunner candidates enabling scaling for future technology nodes. However it poses the common challenges of ‘pattern roughness’ and ‘etch resistance’ aspect which are getting even more critical as we work on smaller dimension features. Continuous efforts are ongoing to improve resist materials and lithography process but the industry is slowly moving to introduce it at high volume manufacturing. Plasma Etch processes have the potential to improvise upon the incoming pattern roughness and provide improved LER/LWR downstream to expedite EUV progress. In this work we demonstrate the specific role of passivation control in the dualfrequency Capacitively Coupled Plasma (CCP) for EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for line/space patterns. We draw the implicit commonalities between different passivation chemistry and their effectiveness for roughness improvement. The effect of relative C:F and C:H ratio in feed gas on CFx and CHx plasma species and in turn the evolution of pattern roughness is drawn. Data that shows the role of plasma etch parameters impacting the key patterning metrics of CD, resist selectivity and LER/LWR is presented.
With shrinking critical dimensions, minimizing each of aspect ratio dependent etching (ARDE), bowing, undercut, selectivity, and within die uniformly across a wafer is met by trading off one requirement against another. The problem of trade-offs is especially critical. At the root of the problem is that roles radical flux, ion flux and ion energy play may be both good and bad. Increasing one parameter helps meeting one requirement but hinders meeting the other. Managing process by managing flux ratios and ion energy alone with conventional sources is not adequate because surface chemistry is uncontrollable. At the root of lack of control is that the electron energy distribution function (<i>eedf</i>) has not been controlled. Fortunately the high density surface wave sources control the <i>eedf</i> by fiat. High density surface wave sources are characterized by distinct plasma regions: an active plasma generation region with high electron temperature (T<sub>e</sub>) and an ionization free but chemistry rich diffusive region (low T<sub>e</sub> region). Pressure aids is segregating the regions by proving a means for momentum relaxation between the source and downstream region. “Spatial pulsing” allows access to plasma chemistry with reasonably high ion flux, from the active plasma generation region, just above the wafer. Low plasma potential enables precise passivation of surfaces which is critical for atomic layer etch (ALE) or high precision etch where the roles of plasma species can be limited to their purposed roles. High precision etch need not be at the cost of speed and manufacturability. Large ion flux at precisely controlled ion energy with RLSATM realizes fast desorption steps for ALE without compromising process throughput and precision.
Patterning the desired narrow pitch at 10nm technology node and beyond, necessitates employment of either extreme ultra violet (EUV) lithography or multi-patterning solutions based on 193nm-immersion lithography. With enormous challenges being faced in getting EUV lithography ready for production, multi-patterning solutions that leverage the already installed base of 193nm-immersion-lithography are poised to become the industry norm for 10 and 7nm technology nodes. For patterning sub-40nm pitch line/space features, self-aligned quadruple patterning (SAQP) with resist pattern as the first mandrel shows significant cost as well as design benefit, as compared to EUV lithography or other multi-patterning techniques. One of the most critical steps in this patterning scheme is the resist mandrel definition step which involves trimming / reformation of resist profile via plasma etch for achieving appropriate pitch after the final pattern. Being the first mandrel, the requirements for the Line Edge Roughness (LER) / Line Width Roughness (LWR); critical dimension uniformity (CDU); and profile in 3-dimensions for the resist trim / reformation etch is extremely aggressive. <p> </p>In this paper we highlight the unique challenges associated in developing resist trim / reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.
Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is
viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated
metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon
gate etch , , , . These wafer-level CD control systems have shown the ability to significantly reduce CD
variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical
performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty
of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of
litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that
the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This
paper will examine the current relationship between litho and etch profile control, determine potential limitations for
future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output