Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production
CMOS electronics will enable new design paradigms for existing system architectures and open new
opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint,
weight, and power consumption of today's communication systems. While broadband analog system applications
represent a smaller volume market than that for digital data transmission, there are significant deployments of analog
electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block
in optical analog signal processing and also could have significant applications in digital communication systems.
Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma
dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges
and opportunities for analog signal processing since the index and
propagation loss change within the waveguide during
modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques
for optical modulation.
Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate
complimentary materials and process sequences required for high index contrast photonic components all within a single
CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits
at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the
Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems,
Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the
latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit
Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical
tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode
photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer
application. This presentation will review the latest advances of the passive and active photonic devices developed and
the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for
optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.
The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.
In this paper, we demonstrate the feasibility of using on-chip optoelectronics within VLSI systems to address a wide range of signal distribution issues by examining the following fundamental question: how can we transmit information from one source to many destinations while minimizing propagation delay, skew, jitter, and noise in a way that is compatible with low-cost manufacturing and CMOS circuits? Example systems with such information distribution requirements include banked arrayable memories such as a DRAM or a dense imager with scanned high speed readout, or a clock distribution system. In all instances individual lines are typically connnected to thousands of gates, slowing cell access times and generating skew. We demonstrate how the use of on-chip photonics within VLSI systems can reduce delays introduced by electrical wires in system-on-a-chip interconnects, busses, caches, and control lines at distances shorter than one meter and as short as a few millimeters. We also describe and demonstrate how a simple on-chip optoelectronic system addressing these problems can be realized at low cost, with monolithic photodetectors and on-chip waveguides in a commercial CMOS process, benefiting both ultra-short and one meter link architectures. This unexplored signal distribution architecture promises high optical to electrical efficiency, low noise, and the benefits of monolithic photodetection not previously achieved in existing approaches.
In this work, we demonstrated a practical means to construct wafer-level optical interconnects in commercial BiCMOS electronics. Through modifying the layout and design of commercially available SiGe Heterojunction Bipolar Transistors (HBT) through MOSISTM foundry, we obtained high performance SiGe Heterojunction Phototransistors (HPT) that utilize the SiGe Base and Collector junction for photo-detection and the transistor action for the amplified photocurrent. Responsivities of 2.4A/W and 0.2A/W were achieved for the phototransistor detecting light of 850nm and 1060nm, respectively. The external quantum efficiency of 350% was obtained. The photocurrent gain was shown to be 78. Furthermore, we investigated the integration of optical waveguides and elements with the SiGe commercial platform to demonstrate an effective approach of the wafer-level optical interconnects. The leaky-mode waveguide routed on the chip surface can couple the light laterally from the input fiber to the buried photodetection region. A 20% coupling efficiency is obtained in the SiGe layer, and provides a response about 40 times higher than that of the vertical illumination. The integrated on-chip waveguides and photodetectors in the commercial platform offer efficient optical-to-electrical conversion and a low-loss routing scheme useful for on-chip computational architectures.
8×8 parallel-channeled optical interconnect systems operating at 1 Gbits/s per channel were designed and developed using complimentary metal-oxide-semiconductor (CMOS) circuits driven 850-nm vertical-cavity surface-emitting laser (VCSEL) arrays and the corresponding photodetector arrays. Low operating threshold and voltage were adapted and facilitated in the design and fabrication of VCSELs and photodetectors in order to achieve the low-power consumption for the entire system. The driver and receiver circuits were fabricated on transparent sapphire substrates using 0.5-μm ultra-thin silicon-on-sapphire (SOS) technology and subsequently flip-chip bonded with corresponding VCSEL and photodetector arrays. The VCSEL transmitter and photoreceiver arrays were biased at 3.3 V and optically coupled in a free-space configuration using compound lens systems. Data communications at bandwidth up to 1.0 Gb/s for each single channel were characterized. Bit-error-rate (BER) was measured to be better than 10-9 from the eye diagrams. Such interconnect systems were also demonstrated for optical data processing using diffractive optical elements.