The key challenge to enable a good defectivity control for extreme ultraviolet (EUV) single expose at 32nm pitch is to understand what are the main drivers for defect generation.
CD is one of the main contributors, and has many sources of variability (reticle, imaging, die layout, scanner).
The paper will first discuss the quantification of defectivity sensitivity to CD, and identification of the main sources of CD variations (EUV flare, black border, etch, APC, mask bias etc...). All those effects do not have the same consequences on the defect level (only nanobridges will be considered as they are the main defect type).
At this pitch, CD margin is becoming critical, an any small variation can lead to pattern collapse/bridge regime.
In a second part, we will discuss the different options for a better CD control and evaluate their impact on the overall defectivity level (reticle, process and tool will be considered).
An Intrafield CD uniformity improvement of 40% can lead to a defect density reduction by about 30%.
Extreme ultraviolet (EUV) materials are deemed as critical to enable and extend the EUV lithography technology. Currently both chemically amplified resist (CAR) and metal-oxide resist (MOR) platforms are candidates to print tight features on wafer, however patterning requirements, process tonality (positive or negative), illumination settings and reticle tonality (dark or bright) play a fundamental role on the material performance and in consequence on the material choice.
In this work we focus on the patterning of staggered pillars using a single EUV exposure, and this by looking at the lithographic and etching performance of CAR and MOR platforms, using metrics as process window, local critical dimension uniformity (LCDU), pillar edge roughness (PER), pillar placement error (PPE) and (stochastic) nano-failures.
As a bright field reticle shows a lower aerial image contrast to print pillars compared to the aerial image of contact holes using a dark field reticle, we also investigate alternative patterning solutions such as the tone reversal process (TRP) to pattern pillars from contact holes.
While the semiconductor industry has reached the high-volume manufacturing of the 7 nm technology node (N7), patterning processes for future technology nodes N5, N3 and even below, are being investigated and developed by research centers. To achieve the critical dimensions of gratings for these future technology nodes, we require multipatterning approaches, such as self-aligned double/quadruple/octuple patterning (SADP/SAQP/SAOP) and multiple litho-etch (LE) patterning, in combination with 193i lithography and even EUV lithography. These gratings need to be subsequently cut or blocked, which is typically done by one or more block masks. As the edge placement error (EPE) budget drastically decreases with decreasing critical dimensions, the standard LE block patterning scheme is not sufficient anymore. To relax the EPE budget, dedicated scaling boosters are required such as the self-aligned block scheme, which defines blocks in trenches, selectively to the neighboring trenches.
In this work we explore the different multipatterning options for lines and blocks at pitches below 20 nm. As such, we will demonstrate and compare three different patterning options to enable 16 nm pitch gratings: 193i-based SAOP, EUV-based SADP and EUV-based SAQP. Finally, we will also elaborate on a self-aligned patterning scheme which does not define lines and blocks sequentially anymore but integrates them in a mixed mode. This patterning approach (SALELE) makes use of two LE masks and two self-aligned block masks. We will present its development status at relaxed pitch (28 nm) and discuss its advantages for future technology nodes.