Variability of digital integrated circuits is becoming an increasing concern with shrinking transistor geometries due to process scaling. As a result, the electrical properties of MOS devices can exhibit significant deviation from their design specifications, causing substantial variation in the performance of high-end designs. Lithography perturbations can affect a number of layout geometries, although the most critical parameter for circuit performance is the transistor channel length or Critical Dimension (CD). Key sources of CD variation include dose, focus, lens aberration and mask errors. In this paper, we compare the impact of above sources of CD variation on circuit performance. We present a new design analysis methodology which models the CD variation from each individual source in static timing analysis for different circuit blocks. Using this analysis capability, we study the impact of lithographic perturbations on block-level circuit performance for two adders. Furthermore, we study the correlation between the CD variability resulting from a lithographic perturbation source, and the resulting circuit performance variability. Through this analysis we determine the suitability of CD variability as an accurate predictor for circuit performance.
We describe a numerical model for chip level lithography variability analysis. Gate level critical dimensions are adjusted based on lithographic variability simulations and these perturbed gate lengths are input to a chip timing analyzer. Statistical modeling studies highlight the interaction between lithography variability and chip timing performance including the role of lithography error correlation length, optical proximity effect residuals, exposure system imperfections and photomask errors. Understanding these relationships is a critical building block for lithographic error tolerancing, design manufacturability improvement and lithography limited yield enhancements on integrated circuits for which timing is a key performance metric.