As part of the National Agenda for Quantum Technology, QuTech (TU Delft and TNO) has agreed to make quantum technology accessible to society and industry via its full-stack prototype: Quantum Inspire. This system includes two different types of programmable quantum chips: circuits made from superconducting materials (transmons), and circuits made from silicon-based materials that localize and control single-electron spins (spin qubits). Silicon-based spin qubits are a natural match to the semiconductor manufacturing community, and several industrial fabrication facilities are already producing spin-qubit chips. Here, we discuss our latest results in spin-qubit technology and highlight where the semiconducting community has opportunities to drive the field forward. Specifically, developments in the following areas would enable fabrication of more powerful spin-qubit based quantum computing devices: circuit design rules implementing cryogenic device physics models, high-fidelity gate patterning of low resistance or superconducting metals, gate-oxide defect mitigation in relevant materials, silicon-germanium heterostructure optimization, and accurate magnetic field generation from on-chip micromagnets.
The mission of QuTech is to bring quantum technology to industry and society by translating fundamental scientific research into applied research. To this end we are developing Quantum Inspire (QI), a full-stack quantum computer prototype for future co-development and collaborative R&D in quantum computing. A prerelease of this prototype system is already offering the public cloud-based access to QuTech technologies such as a programmable quantum computer simulator (with up to 31 qubits) and tutorials and user background knowledge on quantum information science (www.quantum-inspire.com). Access to a programmable CMOS-compatible Silicon spin qubit-based quantum processor will be provided in the next deployment phase. The first generation of QI’s quantum processors consists of a double quantum dot hosted in an in-house grown SiGe/28Si/SiGe heterostructure, and defined with a single layer of Al gates. Here we give an overview of important aspects of the QI full-stack. We illustrate QI’s modular system architecture and we will touch on parts of the manufacturing and electrical characterization of its first generation two spin qubit quantum processor unit. We close with a section on QI’s qubit calibration framework. The definition of a single qubit Pauli X gate is chosen as concrete example of the matching of an experiment to a component of the circuit model for quantum computation.
A CMOS compatible Ge photodetector (Ge-PD) fabricated on Si substrates has been shown to be suitable for near infrared (NIR) sensing; linear and avalanche detection, in both proportional and Geiger modes have been demonstrated, for photon counting at room temperature [1]. This paper focuses on implementations of the technology for the fabrication of imaging arrays of such detectors with high reproducibility and yield. The process involves selective chemical vapor deposition (CVD) of a ~ 1-μm-thick n-type Ge crystal on a Si substrate at 700°C, followed by deposition of a nm-thin Ga and B layer-stack (so-called PureGaB), all in the same deposition cycle. The PureGaB layer fulfills two functions; firstly, the Ga forms an ultrashallow p+n junction on the surface of Ge islands that allows highly sensitive NIR photodiode detection in the Ge itself; secondly, the B-layer forms a barrier that protects the Ge/Ga layers against oxidation when exposed to air and against spiking during metallization. A design for patterning the surrounding oxide is developed to ensure a uniform selective growth of the Ge crystalline islands so that the wafer surface remains flat over the whole array and any Ge nucleation on SiO2 surface is avoided. This design can deliver pixel sizes up to 30×30 μm2 with a Ge fill factor of up to 95 %. An Al metallization is used to contact each of the photodiodes to metal pads located outside the array area. A new process module has been developed for removing the Al metal on the Ge-islands to create an oxide-covered PureGaB-only front-entrance window without damaging the ultrashallow junction; thus the sensitivity to front-side illumination is maximized, especially at short wavelengths. The electrical I-V characteristics of each photodetector pixel are, to our knowledge, the best reported in literature with ideality factors of ~1.05 with Ion/Ioff ratios of 108. The uniformity is good and the yield is close to 100% over the whole array.
The Ge APD detectors are fabricated on Si by using a selective chemical-vapor deposition (CVD) epitaxial growth
technique. A novel processing procedure was developed for the p+ Ge surface doping by a sequence of pure-Ga and
pure-B depositions (PureGaB). Then, PVD Al is used to contact the n-type Si and the anode of p+n Ge diode. Arrays of
diodes with different areas, as large as 40×40 μm2, were fabricated. The resulting p+n diodes have exceptionally good IV
characteristics with ideality factor of ~1.1 and low saturation currents. The devices can be fabricated with a range of
breakdown voltages from a minimum of 9 V to a maximum of 13 V. They can be operated both in proportional and in
Geiger mode, and exhibit relatively low dark counts, as low as 10 kHz at 1 V excess reverse bias. The dark current at 1 V
reverse bias are as low as 2 pA and 20 pA for a 2×2 μm2 and 2×20 μm2 devices, respectively. Higher IR-induced current
than that induced by visible light confirms the sensitivity of Ge photodiodes at room temperature. The 25% peak in Id/Iref
at an IR-wavelength of 1100 nm in Geiger mode is measured for excess bias voltages of 3 V and 4 V, where Id refers to
the photocurrent of the 2×20 μm2 device at different wavelengths, and Iref is the reference photodiode current. The timing
response (Jitter) for the APD when exposed to a pulsed laser at 637 nm and 1 V excess bias is measured as 900 ps at full
width of half maximum (FWHM).
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