Within our paper we are going to discuss the variation within the patterning process in the context of the overall electrical parameter variation in an advanced logic Fab. The evaluation is based on both the variation of ring oscillators that are distributed across the chip as well as on local variation of matched transistor pairs. Starting with a view back to the 130nm technology, we will show how things and requirements changed over time. In particular we focus on the gate layer where we do a detailed ACLV-comparison from the 130nm technology node down to today's 45nm node. Within the patterning variation we keep special attention on the mask performance. Within that section, we do a detailed wafer-mask correlation analysis. Additionally to the low-MEEF gate layer we show the importance of the mask CD-performance for a typical high MEEF-layer. Finally, we discuss the mask contribution to the overall overlay error for the most critical contact to gate overlay. In all of the cases, we will show that the mask performance is not the limiter within today's most advanced technology, as long as we get access to a world class mask shop.
The identification of OPC induced litho hotspots within the product design is essential and a must to make sure
that a new OPC model is working correctly and does no harm to the design and future product.
Several techniques and methods for OPC verification and identification of hotspots are known and long adopted
within the field. An optical rule check done by the simulation software after OPC is one way of identifying
hotspots within the design of the whole chip. This is typically done by using a DRC-type width or space check on
simulation contours (nominal exposure contour or process window contours). However, the pass/fail nature of this
check at a single CD value requires good calibration of the simulation model to avoid false positives and ease of
disposition at tapeout. Another method is the process window qualification method which uses the defect
inspection of a focus exposure matrix wafer for OPC hotspot identification. However, this can not be done prior to
ordering a mask.
Based on a 45nm line space layer OPC qualification, we will demonstrate how optical rule check and process
window qualification is performed, what the individual results will be, and how they can be used for OPC quality
evaluation. The general goal of this work is to show the capabilities of optical rule check and process window
qualification, compare both methods, and detect limitations.
This paper studies the impact of shape and local environment (pattern layout) on the ability to detect defects on the
reticle and the extent to which they affect the dimension of the printed image on the wafer. The authors have made
extensive use of design information to perform a thorough evaluation. OPC software was used to generate mask data that
was comparable to product mask data. Defects were placed on the post-OPC layout and OPC software was also used to
simulate the dimension of the defective features as printed on the wafer. "Design Based Metrology" was used to create
accurate metrology recipes to support wafer and mask metrology. Ultimately the procedures described in this paper
allow a direct correlation to be made between reticle inspectability and the impact of the same defects on wafer CD. Data
is presented for the case of the Contact Hole layer of a "65nm" Logic technology, though the methods described in the
paper are applicable to all layers.
Mask inspection and qualification is a must for wafer fabs to ensure and guarantee high and stable yields. Single defect events can easily cause a million dollar loss through a defect duplicating onto the wafer. Several techniques and methods for mask qualification within a wafer fab are known but not all of them are neither used nor understood regarding their limitations. Increasing effort on existing tool platforms is necessary to detect the defects of interest which are at the limit of the tools specification - On the other hand next generation tools are very sensitive and therefore consume only a negligible amount of time for recipe optimization. Knowing the limits of each inspection tool helps to balance between effort and benefit. Masks with programmed defects of 90nm and 65nm design rule were used in order to compare the different available inspection techniques. During the course of this technical work, the authors concentrate mainly on two inspection techniques. The first one inspects the reticle itself using KLA-Tencor's SLF27 (TeraStar) and SL536 (TeraScan) tools. As the reticle gets inspected itself this is the so called "direct" mask defect inspection. The second inspection technique discussed is the "indirect" mask defect inspection which consists of printing the pattern on a blank wafer and use KLA-Tencor's bright-field wafer inspection tool (2xxx series) to inspect the wafer. Data of this work will include description of the techniques, inspection results, defect maps, sensitivity analysis, effort estimation as well as limitations for both techniques for the used design rule.
High resolution mask inspection in advanced wafer fabs is a necessity. Initial and progressive mask defect problem still remains an industry wide mask reliability issue. Defect incidences and its criticality vary significantly among the type of masks, technology node and layer, fab environment and mask usage. A usage and layer based qualification strategy for masks in production need to be adopted in wafer fabs.
With the help of a high-resolution direct reticle inspection, early detection of critical and also non-critical defects at high capture rates is possible. A high-resolution inspection that is capable of providing necessary sensitivity to critical emerging defects (near edge) is very important in advanced nodes. At the same time, a way to disposition (make a go / no-go decision) on these defective masks is also very important. As the impact of these defects will depend on not only their size, but also on their transmission and MEEF, various defect types and characteristics have to be considered.
In this technical report the adoption of such a high-resolution mask inspection system in wafer fab production is presented and discussed. Data on this work will include inspection results from advanced masks, layer and product based inspection pixel assignment, defect disposition and overall wafer fab strategies in day-to-day production towards mask inspection.
Sub-pellicle particle formation continues to be a significant problem in semiconductor fabs. We have previously reported on the identification of various defects detected on reticles after extended use. This paper provides a comprehensive evaluation of various molecular contaminants found on the backside surface of a reticle used in high-volume production. Previously all or most of the photo-induced contaminants were detected under the pellicle. This particular contamination is a white "haze" detected by pre-exposure inspection using KLA-Tencor TeraStar STARlight with Un-patterned Reticle Surface Analysis, (URSA). Chemical analysis was done using Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) and Raman spectroscopy.
The paramount importance of CD-control for logic speed is well recognized. Whereas across wafer-line-width-variation (AWLV) influences the width of the speed distribution, across chip line-width-variation (ACLV) is a dominating factor for device leakage. In our study we will discuss different ACLV-terms based on AMD’s 0.18 and 0.13μm processes. We will show how the variation of different scanner and reticle-parameters affects both random and systematic ACLV-components. We will show that the systematic part either can be dominated by global or layout-specific CD-signature, depending on the reticle manufacturing process, scanner condition and the circuit design. In particular we will discuss the impact of defocus, lens aberrations, illumination uniformity dose accuracy and flare.
Eventually, we will show the response of critical performance parameters of state of the art μPs and we will judge different parameters with respect to their impact on μP-speed. Focus control and flare control are found to be the most critical tasks. We will discuss appropriate methods to ensure both focus and flare don’t affect device performance negatively.