With decreasing pattern sizes the absolute size of acceptable pattern deviations decreases. For mask-makers a
new technology requires a review, which mask design variations print on the wafer under production illumination
conditions and whether these variations can be found reliably (100%) with the current inspection tools. As
defect dispositioning is performed with an AIMS-tool, the critical AIMS values, above which a defect prints
lithographically significant on the wafer, needs to be determined. In this paper we present a detailed sensitivity
analysis for programmed defects on 2 different KLA 5xx tools employing the pixel P90 at various sensitivity
settings in die-to-die transmitted mode. Comparing the inspection results with the wafer prints of the mask
under disar illumination it could be shown that all critical design variations are reliably detected using a state-of-the-art tool setup. Furthermore, AIMS measurements on defects with increasing defect area of various defect
categories were taken under the same illumination conditions as for the wafer prints. The measurements were
evaluated in terms of AIMS intensity variation (AIV). It could be shown that the AIMS results exhibit a linear
behavior if plotted against the square-root area (SRA) of the defects on the mask as obtained from mask SEM
images. A consistent lower AIV value was derived for all defect categories.
In case drastic changes need to be made to tool configurations or blank specifications, it is important to know as early as possible under which conditions the tight image placement requirements of future lithography nodes can be achieved. Modeling, such as finite element simulations, can help predict the magnitude of structural and thermal effects before actual manufacturing issues occur, and basic experiments using current tools can readily be conducted to verify the predicted results or perform feasibility tests for future nodes. Using numerical simulations, experimental mask registration, and printing data, the effects on image placement of stressed layer patterning, pellicle attachment, blank dimensional and material tolerances, as well as charging during e-beam writing were investigated for current mask blank specifications. This provides an understanding of the areas that require more work for image placement error budgets to be met and to insure the viability of optical lithography for future nodes.
Different mask manufacturing methods can lead to specific signatures (fingerprints) in registration and CD distribution across the mask blanks. A mix-and-match strategy can thereby cause systematic contributions to the total overlay and CD error on the wafer. As a result, mixing masks between different mask vendors or different mask writing tools is often regarded as detrimental to wafer yields. Especially overlay and CD sensitive structuring layers, like gate and
capacitor layer, it is often preferred to use only one mask vendor and mask making process to cancel out systematic errors. However in reality, due to delivery constraints or other logistics boundary conditions, it would sometimes be preferable to be able to mix-and-match for different masks. That could be the case if one manufacturing site is not able to supply a specific type or spec class. On top of that, it might even be required that different copies of one layer are supplied by different vendors. That could be caused by commercial reasons or by switching the mask vendor. In this paper we investigate systematically the influence of mix-and-match masks on frontend wafer yields. Three main issues can be identified as potential pitfalls: registration fingerprints, CD characteristics (linearity, line-end-shortening, proximity), and metrology matching. Main contributors for differences are the writer technology (tool-type, correction settings), developer and etch process, as well as different calibration and metrology methods. The CD characteristic can be compensated by generating appropriate OPC models, and the metrology- and correction methods can be matched. Consequently, we would like to focus on the registration fingerprint of different writer tools from different maskshops as the one systematic contribution which cannot be eliminated. We will investigate the impact of registration fingerprints by analyzing the electrical performance of memory chips.
CD control is crucial to maximize product yields on 300mm wafers. This is particularly true for DRAM frontend lithography layers, like gate level, and deep trench (capacitor) level. In the DRAM process, large areas of the chip are taken up by array structures, which are difficult to structure due to aggressive pitch requirements. Consequently, the lithography process is centered such that the array structures are printed on target. Optical proximity correction is applied to print gate level structures in the periphery circuitry on target. Only slight differences of the different Zernike terms can cause rather large variations of the proximity curves, resulting in a difference of isolated and semi-isolated lines printed on different tools. If the deviations are too large, tool specific OPC is needed. The same is true for deep trench level, where the length to width ratio of elongated contact-like structures is an important parameter to adjust the electrical properties of the chip. Again, masks with specific biases for tools with different Zernikes are needed to optimize product yield. Additionally, mask making contributes to the CD variation of the process. Theoretically, the CD deviation caused by an off-centered mask process can easily eat up the majority of the CD budget of a lithography process. In practice, masks are very often distributed intelligently among production tools, such that lens and mask effects cancel each other. However, only dose adjusting and mask allocation may still result in a high CD variation with large systematical contributions. By adjusting the illumination settings, we have successfully implemented a method to reduce CD variation on our advanced processes. Especially inner and outer sigma for annular illumination, and the numerical aperture, can be optimized to match mask and stepper properties. This process will be shown to overcome slight lens and mask differences effectively. The effects on lithography process windows have to be considered, nonetheless.
This paper discusses a variety of issues encountered in 193nm lithography high volume production. In order to debug the new 193nm technology, a layer from an older qualified technology was qualified on the new tools. Tool statistics were benchmarked against the installed 248nm tool base. Several issues not known from 248nm lithography or from low volume R&D type pilot runs on 193nm were uncovered. Specifically, issues related to aging of optical parts, defects from various sources, track processing, and masks are discussed.