We present a fine-grain parallel processor architecture which considers particularly the requirements defined by future 3-dimensional (3D) stacked optoelectronic devices. The architecture concept is well-suited for novel detector arrays which are exploited in data communication applications based on high-speed VCSEL photonic interconnects as well as for optical sensing applications in smart CMOS camera chips. We assume the presence of a two-dimensional optoelectronic interface mounted on top of the stacked device. Such a vertical communication scheme is perfect for the realization of very compact and fast working devices in embedded systems, e.g. in gripper arms of robots.
We present a chip, which is suited for applications in data-communication areas as well as in image-processing applications. Through the combination of parallel signal gathering and processing, we save components and we can increase the processing rate. We think thereby on problems like pre processing in camera systems also called "intelligent sensor". The chip has a structure as follows. Every processor element contains an optical detector, a trans-impedance amplifier and a comparator. A digital logic is directly connected to these components. This logic realizes the programmable processing of the signals. Each processor element is connected to its four direct orthogonal neighbours within the processor array. The digital parts consist of a special processor. It realises simple hard-wired image algorithms. As an example for cooperation of the analogue and digital part we have implemented some morphologic operations. Our receiver consists of a 8×8 photodiode array. A data rate of 625 Mbit/s for an average optical power in the range of 25 µW to 500 µW is possible for a bit-error-rate of 10-9 per channel. Signal processing limits the frequency to 200 MHz for a processor element according to simulations. Using an image with a size of 6×6 according to parallel data transfer a data throughput of 7.2 GHz results.
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8'8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 µm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.