We show how combining machine learning with physical models can improve the overall accuracy of modeling the lithographic process for OPC applications by up to 40%. This level of model accuracy improvement is critical to meet the stringent requirements of the 5nm node and below. We demonstrate how the judicious design of the neural network can create a model capable of high accuracy and high contour quality, even when no contour data is available. This allows the neural network model to be introduced without disrupting the model calibration flow used in OPC.
Critical edge placement margins continue to shrink in advanced designs, Over the years, various methods have been used to quantify the lithographic “process window”, often in terms of allowable CD variation. Ultimately however, what is of most interest is the margin for chip failure, either due to hard pinching, bridging, or pattern collapse of a single layer, or interlayer critical edge placement errors. The latter could include insufficient overlap between layers such as metal and via, or unwanted bridging of patterns between layers. We present here a framework for estimating the failure rate for any individual feature given an assumed manufacturing distribution of primary patterning variables such as dose, focus, mask dimension, and perhaps overlay. If the failure rate for all features within the die is known, then by extension the failure rate for the entire die can be known. Since estimating the process window exhaustively for all in-die locations is not possible, we first identify process window limiting features, then utilize this knowledge to estimate overall die failure rates. This method can account for both systematic failure of an individual feature instance as well as stochastic failure for repeating patterns.
As nodes become smaller and smaller, the OPC applied to enable these nodes becomes more and more sophisticated. This trend peaks today in curve-linear OPC approaches that are currently starting to appear on the roadmap. With this sophistication of OPC, the mask pattern complexity increases. CD-SEM based mask qualification strategies as they are used today are starting to struggle to provide a precise forecast of the printing behavior of a mask on wafer. An aerial image CD measurement performed on ZEISS Wafer-Level CD system (WLCD) is a complementary approach to mask CD-SEMs to judge the lithographical performance of the mask and its critical production features. The advantage of the aerial image is that it includes all optical effects of the mask such as OPC, SRAF, 3D mask effects, once the image is taken under scanner equivalent illumination conditions. Additionally, it reduces the feature complexity and analyzes the printing relevant CD.
Aberration characterization plays a critical role in the development of any optical system. State-of-the-art lithography systems have the tightest aberration tolerances. We present an approach to image-based pupil plane amplitude and phase characterization using models built with a space-domain basis, in which aberration effects are separable. A polynomial model is constructed between the projections of the image intensity for chosen binary mask targets onto this basis and pupil amplitude or phase variation. This method separates model building and pupil characterization into two distinct steps, thus enabling rapid pupil characterization following data collection. The basis is related to both the transmission cross-coefficient function and the principal components of the image intensity. The pupil plane variation of a zone-plate lens from the Semiconductor High-NA Actinic Reticle Review Project (SHARP) at Lawrence Berkeley National Laboratory is examined using this method. Results are compared to pupil plane characterization using a previously proposed methodology where inverse solutions are obtained through an iterative process involving least-squares regression.
The appropriate representation of the photomask in the simulation of wafer lithography processes has been shown to be of vital importance for 14-nm and below . This task is difficult, since accurate optical metrology and physical metrology of the three-dimensional mask structure is not always available. OPC models for wafer patterning comprise representations of the mask, the optics, and the photoresist process. The traditional calibration of these models has involved empirical tuning of model parameters to CD-SEM data from printed photoresist patterns. Such a flow necessarily convolves the resist effects and it has been difficult to reliably obtain mask and optical parameters which are most representative of physical reality due to aliasing effects. In this work, we have undertaken to decouple the mask model from the photoresist process by use of the ZEISS Wafer-Level CD (WLCD) tool based upon aerial image metrology. By measuring the OPC test pattern mask with WLCD, the mask parameters in the OPC model can be tuned directly without interference of resist effects. This work utilized 14-nm,10-nm, and 7-nm node masks, and we demonstrate that the use of such a flow leads to the most predictive overall OPC models, and that the mask parameters resulting from this flow more closely match the expected physical values. More specifically, the mask corner rounding, sidewall angle, and bias values were tuned to the WLCD data instead of the wafer CD SEM data, and resulted in improved predictive capability of the model. Furthermore, other mask variables not traditionally tuned can be verified or tuned by matching simulation to aerial image metrology.
The use of optical proximity correction (OPC) demands increasingly accurate models of the photolithographic process. Model building and analysis techniques in the data science community have seen great strides in the past two decades which make better use of available information. This paper expands upon Bayesian analysis methods for parameter selection in lithographic models by increasing the parameter set and employing posterior predictive checks. Work continues with a Markov chain Monte Carlo (MCMC) search algorithm to generate posterior distributions of parameters. Models now include wafer film stack refractive indices, n and k, as parameters, recognizing the uncertainties associated with these values. Posterior predictive checks are employed as a method to validate parameter vectors discovered by the analysis, akin to cross validation.
We present an approach to image-based pupil plane amplitude and phase characterization using models built with principal component analysis (PCA). PCA is a statistical technique to identify the directions of highest variation (principal components) in a high-dimensional dataset. A polynomial model is constructed between the principal components of through-focus intensity for the chosen binary mask targets and pupil amplitude or phase variation. This method separates model building and pupil characterization into two distinct steps, thus enabling rapid pupil characterization following data collection. The pupil plane variation of a zone-plate lens from the Semiconductor High-NA Actinic Reticle Review Project (SHARP) at Lawrence Berkeley National Laboratory will be examined using this method. Results will be compared to pupil plane characterization using a previously proposed methodology where inverse solutions are obtained through an iterative process involving least-squares regression.
The use of optical proximity correction (OPC) demands increasingly accurate models of the photolithographic process. Model building and inference techniques in the data science community have seen great strides in the past two decades which make better use of available information. This paper aims to demonstrate the predictive power of Bayesian inference as a method for parameter selection in lithographic models by quantifying the uncertainty associated with model inputs and wafer data. Specifically, the method combines the model builder's prior information about each modelling assumption with the maximization of each observation's likelihood as a Student's t-distributed random variable. Through the use of a Markov chain Monte Carlo (MCMC) algorithm, a model's parameter space is explored to find the most credible parameter values. During parameter exploration, the parameters' posterior distributions are generated by applying Bayes' rule, using a likelihood function and the a priori knowledge supplied. The MCMC algorithm used, an affine invariant ensemble sampler (AIES), is implemented by initializing many walkers which semiindependently explore the space. The convergence of these walkers to global maxima of the likelihood volume determine the parameter values' highest density intervals (HDI) to reveal champion models. We show that this method of parameter selection provides insights into the data that traditional methods do not and outline continued experiments to vet the method.
In the field of model design and selection, there is always a risk that a model is over-fit to the data used to train the model. A model is well suited when it describes the physical system and not the stochastic behavior of the particular data collected. K-fold cross validation is a method to check this potential over-fitting to the data by calibrating with k-number of folds in the data, typically between 4 and 10. Model training is a computationally expensive operation, however, and given a wide choice of candidate models, calibrating each one repeatedly becomes prohibitively time consuming. Akaike information criterion (AIC) is an information-theoretic approach to model selection based on the maximized log-likelihood for a given model that only needs a single calibration per model. It is used in this study to demonstrate model ranking and selection among compact resist modelforms that have various numbers and types of terms to describe photoresist behavior. It is shown that there is a good correspondence of AIC to K-fold cross validation in selecting the best modelform, and it is further shown that over-fitting is, in most cases, not indicated. In modelforms with more than 40 fitting parameters, the size of the calibration data set benefits from additional parameters, statistically validating the model complexity.
Significant interest from the integrated circuit (IC) industry has been placed on directed selfassembly (DSA) for sub 10nm nodes. DSA is being considered as a cost reduction complementary process to multiple patterning (MP) and an enabler of new technology nodes. However, to realize the potential of this technology, it is essential to look holistically at the necessary infrastructure from the point of view of materials, hardware, software, process integration and design methodologies which enable its deployment in large volume manufacturing. One key aspect in enabling DSA processes is the ability to mirror functionality of full chip mask synthesis and verification methods of existing tools used in production. One of those critical components is the ability to accurately model the placement of the target phases in the DSA process with a given mask shape, as well as determining the conditions at which unwanted phase transitions start to occur. Self-consistent field theory and Monte Carlo1 simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. The nature of a compact model is to make a series of approximations allowing a simpler description of the problem in a way that the phenomena of interest can be sufficiently captured even if it is at the expense of its generality. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-PMMA diblock copolymer system needs. The processes uses etched short trenches as guiding patterns in which the vertical DSA cylinders are formed. By focusing in the phase of interest (i.e., cylinder forming conditions), it is possible to reformulate the problem in a phenomenological formulation which accounts for the interaction among cylinders, the volume fraction of the respective co-polymers and the interaction with the confinement walls. As such, a 2D approximation to the 3D environment can be applied too simplify thhe representation of the DSA process. This enables thee use of a 2D contour for compact model training and verification. Further simplification is not recommended due to the nature of the grapho-epitaxy guiding patterns, where a simple CD measurement is not sufficient to capture the 2D environment of post routed contact patterns for sub 10nm nodes. In this paper, we will study the application of the DSA compact model to a via layer of imec’s 7nm technology node standard cells. ArF immersion lithography will be used to pattern the guides, and the layout will be DSA compliant to determine the mask complexity as well as the sensitivity of the solution to mask biases for the contact layer.
EUV lithography is likely more sensitive to drift from thermal and degradation effects than optical counterparts. We have developed an automated approach to photoresist image-based aberration metrology. The approach uses binary or phase mask targets and iterative simulation based solutions to retrieve an aberrated pupil function. It is well known that a partially coherent source both allows for the diffraction information of smaller features to be collected by the condenser system, and introduces pupil averaging. In general, smaller features are more sensitive to aberrations than larger features, so there is a trade-off between target sensitivity and printability. Therefore, metrology targets using this technique must be optimized for maximum sensitivity with each illumination system. This study examines aberration metrology target optimization and suggests an optimization scheme for use with any source. Interrogation of both low and high order aberrations is considered. High order aberration terms are interrogated using two separate fitting algorithms. While the optimized targets do show the lowest RMS error under the test conditions, a desirable RMS error is not achieved by either high order interrogation scheme. The implementation of a previously developed algorithm for image-based aberration metrology is used to support this work.
As EUV lithography attempts to outperform other lithographical methods to the sub-14 nm node, the demand for a larger NA traditionally dominates the drive for scaling. There are, however, many challenges to overcome in order to accomplish this . Due to the reflective optics in EUV systems, angular effects of oblique illumination, and non-zero chief ray angle at the objective (CRAO), must be carefully considered and will need to be well understood if high-NA EUV is to be successful. This study investigates impact on of the bias between horizontal and vertical feature CD, image placement error and NILS. Effects of sidewall absorber angle, absorption coefficient (k) and absorber thickness are observed through pitch with various source shapes in an EUV lithography system.
Historically IC (integrated circuit) device scaling has bridged the gap between technology nodes. Device size reduction
is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Exemplifying
this trend are aggressive reductions in memory cell sizes that have resulted in systems with diminishing area between
bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently
difficult to resolve because of their relatively small area and complex aerial image. To accommodate these trends,
semiconductor device design has shifted toward the implementation of elliptical contact features. This empowers
designers to maximize the use of free device space, preserving contact area and effectively reducing the via dimension
just along a single axis. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect
ratio vias for implementation in electronic design systems. Vortex masks, characterized by their helically induced
propagation of light and consequent dark core, afford great potential for the patterning of such features when coupled
with a high resolution negative tone resist system. This study investigates the integration of a vortex mask in a 193nm
immersion (193i) lithography system and qualifies its ability to augment aspect ratio through feature density using aerial
image vector simulation. It was found that vortex fabricated vias provide a distinct resolution advantage over
traditionally patterned contact features employing a 6% attenuated phase shift mask (APM). 1:1 features were
resolvable at 110nm pitch with a 38nm critical dimension (CD) and 110nm depth of focus (DOF) at 10% exposure
latitude (EL). Furthermore, iterative source-mask optimization was executed as means to augment aspect ratio. By
employing mask asymmetries and directionally biased sources aspect ratios ranging between 1:1 and 2:1 were
achievable, however, this range is ultimately dictated by pitch employed.