Improvements in repair process, software, and AFM tip technology have brought about an overall 2D shape
reconstruction capability to nanomachining that has not been previously imagined. Repair results are shown
for various processes to highlight their relative strengths and weaknesses. The impact of technical
improvements is shown in the advances in repair dimensional precision and overall imaging performance. The
greater technical potential of nanomachining is realized in this examination for mask repair scaled to smaller
repair geometries while repairing larger defects that may span these critical patterns.
Reduced design rules demand higher sensitivity of inspection, and thus small defects which did not affect printability
before require repair now. The trend is expected to be similar in extreme ultraviolet lithography (EUVL) which is a
promising candidate for sub 32 nm node devices due to high printing resolution. The appropriate repair tool for the small
defects is a nanomachining system. An area which remains to be studied is the nano-machining system performance
regarding repair of the defects without causing multilayer damage. Currently, nanomachining Z-depth controllability is 3
nm while the Ru-capping layer is 2.5 nm thick in a Buffer-less Ru-capped EUV mask. For this report, new repair
processes are studied in conjunction with the machining behavior of the different EUVL mask layers. Repair applications
to achieve the Edge Placement(EP) and Z-depth controllability for an optimal printability process window are discussed.
Repair feasibility was determined using a EUV micro exposure tool (MET) and Actinic Imaging Tool (AIT) to evaluate
repairs the 30 nm and 40 nm nodes. Finally, we will report the process margin of the repair through Slitho-EUVTM
simulation by controlling side wall angle, Z-depth, and EP (Edge Placement) on the base of 3-dimensional experimental
The transition to sub 45 nm technology nodes presents a significant technical challenge for mask repair due to a number of
previously lesser known physical phenomena. Nanomachining technology, which has a history of equally successful repair
of all photomask types-including Cr binary masks, has not been immune to these challenges. This has led to the
development of a number of distinctly new processes to meet these technical requirements. In one of the two new processes
reviewed in this work, the bulk of the defect is removed by applying compressive instead of tangential stresses to the
NanoBitTM during repair. This allows for 45 nm and smaller repairs, with sidewall angles and aspect ratios greater than 70°
and 2:1 respectively, in open mask structures. For repair in closed-or missing defect-structures, a process was developed to
minimize tip deflection away from the designated repair box boundaries for accurate two dimensional shape reconstructions
of deep and complex patterns. The successful application of this technique is shown for actinic phase-correct missing and
partial CPL, EAPSM, and Cr-absorber square contacts at these nodes. Additionally, the potential of these new processes to
enable higher aspect advanced NanoBitTM designs for robust mask repair, and the new processes developed to effectively
clean nanomachining debris from these advanced mask structures are discussed to provide a complete review of these
solutions and their supporting technologies.
The majority of trends in lithography technology necessitate the use of smaller, higher aspect, patterns on
photomasks which are increasingly sensitive to traditional cleaning processes. Particle defects are of increasing
concern since, in deep and even overhanging structures, they can become fixed to the surface with such strength
that any traditional cleaning technique would destroy any small, high-aspect, mask structures. A series of
advanced new solutions are presented here which have been shown to remove these types of problem particles as
applied to 45 nm node nanomachining mask repair with a RAVE nm450 system. In the first method, a cryogenic
cleaning system is modified to greatly enhance selective removal of nanoparticles from high aspect structures. In
the second method, the nm450 repair tool itself is applied to selectively remove targeted particles from a nanoscale
area of the mask surface thus only affecting the region of interest and not touching any sensitive surrounding
surfaces or structures.
Recently questions have been raised about whether high aspect ratio (HAR) NanoBitsTM can be effectively utilized to
repair extension defects in 45 nm node and beyond. The primary concern has been how the effect of NanoBitTM
deflection impacts edge placement, sidewall angle and z-depth control repeatability. Higher aspect ratio bits are required
for defects that arise as mask feature sizes become smaller. As the aspect ratio of the NanoBitTM continues to increase to
meet these demands, the cross sectional area of the bit used for nanomachining becomes thinner and more susceptible to
bending under the forces applied during the nanomachining process. This is especially true when deeper features that
require HAR NanoBitsTM are being repaired. To overcome this trend RAVE LLC has developed a new repair process
that utilizes the strength of the bit shape. Repair of 45 nm node defects that require HAR NanoBitsTM will be
demonstrated using a new repair process and cantilever design.
As mask complexity has increased and design rules continued to shrink, the manufacturing cost per mask has steadily
increased as well. Studies also show that defects are the number one issue for mask yield. Smaller defects are typically
addressed through process development, or through photomask repair. The occurrence of large defects often may only
be further reduced through use of expensive clean room improvements, like SMIF handling systems. The impact of each
large defect therefore increases while the feasibility in their repair decreases as they can span a large number of adjoining
densely packed patterns. The presence of sub-resolution features such as scatter bars and the increasing use of embedded
phase-shifting masks also complicates the timely repair of such defects.
Existing mask repair techniques such as nanomachining, electron beam, or focused ion beam are challenged to produce
high yield repairs on such large defects within a reasonable timeframe. Often very complex repairs may in fact take
longer than a rewrite of the mask! Deep UV (DUV) femtosecond pulse laser mask repair provides a unique solution to
this defect repair need.
Methods and results are discussed for the process optimization for the removal of large (5μm) area repair on both Cr and
MoSi absorber films on quartz. Additionally, high repair throughput results are shown for unknown contamination
removal, and reproduction of ≥1 μm complex unconnected patterns in a single repair run lasting a matter of minutes.
Closed-loop CD feedback in-situ with the iterative repair process for such structures can readily result in an edge
placement control within ±15 nm. Prior iterative CD closed-loop repairs on specific structures have reliably yielded
results within ±10 nm, as confirmed by AIMS CD error, even after aggressive mask wet clean. The nanometer scale
dimensional resolution and repeatability of such repairs is shown with the use of sub-pixel resolution automated pattern
reconstruction using integrated high-NA DUV microscope imaging.
Photomask repair has been acknowledged as a value creation step in the mask process flow. As technology pushes forward, the need for more advanced mask repair is apparent. This paper introduces a new mask repair tool directed at the 65 nm node and extendable to the 45 nm node, the nm650de (digital extendible). The system provides high throughput, advanced imaging capabilities, tight control in X, Y, and minimal Z drift with very low noise. Results are shown for the repair of edge defects in tight lines and spaces on both Cr binary and MoSi (EPSM) masks. Statistical analysis is conducted with respect to edge placement, surface damage, and 193 nm AIMSTM, "transmission" (relative normalized peak intensity). This analysis is then compared to specifications for each technology node.