Double patterning (DP) has become the most likely candidate to extend immersion lithography to the 32 nm node and
beyond. This paper focuses on experimental results of 32nm half pitch patterning using NSR-S620D, the latest Nikon
ArF immersion scanner. A litho-freeze-litho (LFL) process was employed for this experiment. Experimental results of
line CDU, space CDU, and overlay accuracy are presented. Finally, a budget for pitch splitting DP at the 22 nm half
pitch is presented.
The cost of ownership (CoO) of candidate technologies for 22 nm half-pitch lithography is calculated. To more accurately compare technologies with different numbers of process steps, a model that includes deposition, etching, metrology, and other costs is created. For 22 nm half-pitch nodes, extreme ultraviolet lithography (EUVL) has a significant cost advantage over other technologies under certain mask cost assumptions. Double patterning, however, may be competitive under worst-case EUVL mask cost assumptions. Sensitivity studies of EUVL CoO to throughput and uptime show EUVL may be cost-competitive at lower uptime and throughput conditions. Finally, calculation of the CoO of 450 mm lithography shows that the expected cost reduction is between 0% and 15%.
The problem of the alignment tree for double patterning (DP) is presented. When the 2nd DP exposure is aligned to the
underlying zero layer, the space CD uniformity is shown to be well outside the budget for the 32 nm HP node. Aligning
the 2nd DP layer to the zero layer gives better overlay results, but aligning the 2nd DP pattern to the 1st DP pattern gives
results well within the overlay requirements for the 32 nm HP. Aligning the 2nd DP layer to the 1st DP layer is
recommended to give the best CD uniformity and overlay results. Experimental results show, qualitatively, the CD
uniformity is significantly worse when the 2nd pattern is aligned to the zero layer, but the overlay for both alignment trees
could be corrected to roughly the same levels. The raw overlay data shows a significantly different signature for the two
alignment trees, possibly caused by alignment mark signal differences between the marks on the zero and 1st layers, or
distortion of the zero layer after the first etch. The requirements for a DP exposure tool were reviewed and can be
summarized as improved dose control, improved overlay performance, and significantly higher throughput.
Double patterning (DP) is today the main solution to extend immersion lithography to the 32 nm node and beyond. Pitch
splitting process with hardmask transfer and spacer process have been developed at CEA-LETI-Minatec. This paper
focuses on experimental data using dry ArF lithography with a k1 factor of 0.20 ; the relative impact of each DP step on
overlay and CD uniformity budgets is analyzed. In addition, topography issues related to the presence of the patterned
hard mask layer during the second imaging step is also investigated. Tool-to-itself overlay, image placement on the
reticle and wafer deformation induced by this DP process are evaluated experimentally and resulting errors on CD
budget have been determined. CD uniformity error model developed by Nikon describing the relationship between CD
and overlay in different DP processes is validated experimentally.
Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are being considered. This paper focuses on the requirements of the most complex forms of DP, pitch-splitting (where line density is doubled through two exposures) and spacer processes (where a deposition process is used to achieve the final pattern). Budgets for critical dimension uniformity and overlay are presented along with tool and process requirements to achieve these budgets. Experimental results showing 45-nm lines and spaces using dry ArF lithography with a k1 factor of 0.20 are presented to highlight some of the challenges. Finally, alternatives to DP are presented.
Double patterning is recognized as the best candidate for 32 nm half-pitch lithography. Currently pitch splitting processes are being considered for logic processes and spacer processes are being considered for memory. In pitch splitting, errors in overlay between the first and second exposure become CD errors on the final pattern. For this reason, overlay requirements are severe for pitch splitting double patterning. Revised CD and overlay budgets are presented, as well as technical requirements to satisfy these budgets. Spacer processes do not have similar restrictions on overlay, so they can be achieved using current immersion tools. Exposure tool requirements for double patterning are discussed and modifications to current platforms are described.
The cost of ownership (COO) of candidate technologies for 32 nm and 22 nm half-pitch lithography is calculated. To more accurately compare technologies with different numbers of process steps, a model that includes deposition, etching, metrology, and other costs is created. Results show lithography COO for leading edge layers will increase by roughly 50% from the 45 nm to the 32 nm half-pitch nodes. Double patterning and extreme ultraviolet lithography (EUVL) technologies have roughly the same COO under certain conditions. For 22 nm half-pitch nodes, EUVL has a significant cost advantage over other technologies under certain mask cost assumptions. Double patterning, however, may be competitive under worst case EUVL mask cost assumptions. Sensitivity studies of EUVL COO to throughput and uptime show EUVL may be cost-competitive at lower uptime and throughput conditions. In spite of these higher costs, total lithography costs for 32 nm and 22 nm half-pitches remain within reach of the Moore's Law trend. Finally, the COO of 450 mm lithography is calculated and shows the expected cost reduction is between 0% and 15%.
Extending lithography to 32 nm and 22 nm half pitch requires the introduction of new lithography technologies, such as
EUVL or high-index immersion, or new techniques, such as double patterning. All of these techniques introduce large
changes into the single exposure immersion lithography process as used for the 45 nm half pitch node. Therefore, cost
per wafer is a concern. In this paper, total patterning costs are estimated for the 32 nm and 22 nm half pitch nodes
through the application of cost-of-ownership models based on the tool, mask, and process costs. For all cases, the cost of
patterning at 32 nm half pitch for critical layers will be more expensive than in prior generations. Mask costs are
observed to be a significant component of lithography costs even up to a mask usage of 10,000 wafers/mask in most
cases. The more simple structure of EUVL masks reduces the mask cost component and results in EUVL being the most
cost-effective patterning solution under the assumptions of high throughput and good mask blank defect density.
Immersion technology is definitely the mainstream lithography technology for NAND FLASH in recent years since
hyper-NA immersion technology drives the resolution limit down to the 40-50 nm half pitch region. Immersion
defectivity and overlay issues are key challenges before introducing immersion technology into mass production. In this
work, both long term immersion defectivity and overlay data, as well as good photoresist performance, show the Nikon
S610C immersion scanner plus LITHIUS i+ cluster is capable of 40-50 nm NAND FLASH mass production. Immersion
defects are classified based on their causes, and no tool specific immersion defects, e.g. bubbles and water marks, were
found in the Nikon S610C plus TEL LITHIUS i+ cluster. Materials-induced immersion defects require more attention to
achieve production-worthy results.
Nikon's production immersion scanners, including the NSR-S609B and the NSR-S610C, have now been in the field for
over 2 years. With these tools, 55 nm NAND Flash processes became the first immersion production chips in the world,
and 45 nm NAND Flash process development and early production has begun. Several logic processes have also been
developed on these tools. This paper discusses the technical features of Nikon's immersion tools, and their results in
Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half
pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are
being considered. This paper focuses on the requirements of the most complex forms of DP, pitch splitting, where line
density is doubled through two exposures, and sidewall processes, where a deposition process is used to achieve the final
pattern. Budgets for CD uniformity and overlay are presented along with tool and process requirements to achieve these
budgets. Experimental results showing 45 nm lines and spaces using dry ArF lithography with a k1 factor of 0.20 are
presented to highlight some of the challenges. Finally, alternatives to double patterning are presented.
In recent years, manufacturers of high precision mechanical parts have been required to produce increasingly complex designs, in smaller lot sizes, with improved quality. These requirements demand lower process costs, shorter development cycles and more accurate manufacturing technologies. To meet these demands, manufacturers are attempting to both improve process quality and provide better CAD/CAM integration. The technique of on- machine acceptance provides one mechanisms for improving the part inspection and verification process. This approach allows one machine and one process capability model to be used for both fabrication and inspection, reducing capital cost and overall cycle time. However, the on-machine acceptance technique possesses greater potential than as simply an alternative mechanism for verifying part geometry. If the inspection capability information generated by on-machine acceptance processes can be made available to designers, it can be used to create a design-for-inspectability environment and help realize the benefits of concurrent engineering. This paper proposes a novel architecture which integrates on-machine acceptance with an agent-based concurrent design environment, for reducing both the cost and production time for high quality, small lot size, mechanical parts. This work has focused on the production of stainless steel pressure vessels at the Integrated Manufacturing Technology Laboratory manufacturing cell, located at Sandia National Laboratories, California.