SMIC is a pure-play IC foundry, as foundry culture Turn-Around Time is the most important thing FABs concern about. And aggressive tape out schedule required significant reduction of GDS to mask flow run time. So the objective of this work is to evaluate an OPC methodology and integrated mask data preparation flow on runtime performance via so-called 1-IO-tape-out platform. By the way, to achieve fully automated OPC/MDP flow for production. To evaluate, we choose BEOL layers since they were the ones hit most by runtime performance -- not like FEOL, for example, Poly to CT layers there're still some non-critical layers in the between, OPC mask makings & wafer schedules are not so tight. BEOL, like M2, V2,then M3 V3 and so on, critical layer OPC mask comes one by one continuously. Hence, that's why we pick BEOL layers. And the integrated flow we evaluated included 4 layers of metal with MB-OPC and 6 layers of Via with R-B OPC. Our definition of success to this work is to improve runtime performance at least of larger than 2x. At meantime, of course, we can not sacrifice the model accuracy, so maintaining equal or better model accuracy and OPC/mask-data output quality is also a must. For MDP, we also test the advantage of OASIS and compared with GDS format.
Accurately and efficiently verifying the device layout is a crucial step in semiconductor manufacturing. A single missed design violation carries the potential for a disastrous and avoidable yield loss. Typically, design rule checking (DRC) is accomplished by validating drawn layout geometries against pre-determined rules, the specifics of which are derived empirically or from lithographic first principles. These checks are intrinsically rigid, and, taken together, a set of DRC rules only approximate the manufacturable design space in the crudest manner. Process-specific effects are entirely neglected. But for leading-edge technologies, process variations significantly impact the manufacturability of a design, so traditional DRC becomes increasingly difficult to implement, or worse, speciously inaccurate. Fortunately, the rise of Optical Proximity Correction (OPC) has given manufacturers a means to accurately model optical and process effects, and, therefore, an opportunity to introduce this information into the layout validation flow. We demonstrate an enhanced, full-chip DRC technique, which utilizes process models to locate marginal or bad design features and classify them according to severity.
Using a commercialized product Calibre OPC platform, optical and process models were built that accurately predict wafer-level phenomena for a sub-90nm poly process. The model fidelity relative to nominal wafer data demonstrates excellent result, with EPE errors in the range of ±2nm for pitch features and ±7 for line-end features. Furthermore, these models accurately predict defocus and off-dose wafer data. Overlaying SEM images with model-predicted print images for critical structures shows that the models are stable and accurate, even in areas especially prone to pinching or bridging. In addition, process window ORC is shown to identify potential failure points within some representative designs, allowing the mask preparation shop to easily identify these areas within the fractured data. And finally, the data and images of mask hotspots will be shown and compared down to wafer level.
The existing approaches to lithography model generation rely heavily on one-dimensional (1D) Scanning Electron Microscope (SEM) measurements to characterize a two-dimensional (2D) process. Traditional 1-D techniques require measuring an exhaustive test cell matrix containing hundreds of features representing different sizes, shapes, and pitches. Despite the large amount of data collected, there can still be a significant amount of model error present, particularly in 2D structures such as line ends and corners, which do not lend themselves to a well defined CD measurement. This is due to the inadequacy of using a 1D measurement for characterizing 2D features. A new approach to lithography simulation confirms the axiom "a SEM image is worth a thousand CD measurements". Using a set of six or fewer SEM images and fitting a contour-based 2-D simulation to the image during the model derivation, achieves a good 2D predictive capability without sacrificing through pitch predictability. This paper will show the results of using SEM images to tune lithography models on clear and dark field layers and illustrate the accuracy of the models using contour based simulations overlaid with SEM images. This approach to OPC modeling greatly reduces the number of CD measurements required to generate a model and lessens the susceptibility of the model to SEM CD metrology errors, while achieving a very well tuned model. This method works best when the 2-D simulation and calibration are coupled to the algorithms that perform the correction.
A more precise and accurate method of quantifying line end effects on binary photomasks becomes necessary as reticle features continue to decrease in size. A new methodology for measuring and evaluating line ends was developed. By performing multiple step-wise measurements across a single line end feature using a fixed-width region of interest, a simulated representation of the line end profile could be generated. A high n-order polynomial fit was then applied to the resultant data set and a minimum line end value was extrapolated. This methodology reduced the measurement error directly caused by the region-of-interest (ROI) placement and sizing while, at the same time, it improved the accuracy and precision of the measurement. The generated line end profiles may be further used for modeling, simulation, or characterization.
The complexity of current semiconductor technology due to shrinking feature sizes causes more and more engineering efforts and expenses to deliver the final product to customers. One of the largest expense in the entire budget is the reticle manufacturing. With the need to perform mask correction in order to account for optical proximity effects on the wafer level, the reticle expenses have become even more critical. For 0.13um technology one can not avoid optical proximity correction (OPC) procedure for modifying original designs to comply with design rules as required by Front End (FE) and Back End (BE) processes. Once an OPC model is generated one needs to confirm and verify the said model with additional test reticles for every critical layer of the technology. Such a verification procedure would include the most critical layers (two FE layers and four BE layers for the 0.13 technology node). This allows us to evaluate model performance under real production conditions encountered on customer designs. At LSI we have developed and verified the low volume reticle (LVR) approach for verification of different OPC models. The proposed approach allows performing die-to-die reticle defect inspection in addition to checking the printed image on the wafer. It helps finalizing litho and etch process parameters. Processing wafers with overlaying masks for two consecutive BE layer (via and metal2 masks) allowed us to evaluate robustness of OPC models for a wafer stack against both reticle and wafer induced misalignments.
The challenge of delivering acceptable semiconductor products to customers in timely fashion becomes more difficult as design complexity increases. The requirements of current generation designs tax OPC engineers greater than ever before since the readiness of high-quality OPC models can delay new process qualifications or lead to respins, which add to the upward-spiraling costs of new reticle sets, extend time-to-market, and disappoint customers. In their efforts to extend the printability of new designs, OPC engineers generally focus on the data-to-wafer path, ignoring data-to-mask effects almost entirely. However, it is unknown whether reticle makers' disparate processes truly yield comparable reticles, even with identical tools. This approach raises the question of whether a single OPC model is applicable to all reticle vendors. LSI Logic has developed a methodology for quantifying vendor-to-vendor reticle manufacturing differences and adapting OPC models for use at several reticle vendors. This approach allows LSI Logic to easily adapt existing OPC models for use with several reticle vendors and obviates the generation of unnecessary models, allowing OPC engineers to focus their efforts on the most critical layers.