The use of sub-resolution assist features (SRAFs) is a necessary and effective
technique to mitigate the proximity effects resulting from low-k1 imaging with
aggressive illumination schemes. This paper investigates the application of one
implementation of Inverse Lithography Technology (ILT) to determine optimized SRAF
placement and size. In contrast to traditional rule-based methods in which SRAF
placement and size are typically predetermined and frozen in place, unmodified during
OPC, ILT allows for the simultaneous placement and sizing of SRAFs during target
inversion to maximize image quality while also maintaining margin against sidelobe
printing. Furthermore, ILT enables SRAF placement for random as well as periodic
patterns. In this paper, SRAF placement using this approach is studied through
simulations. The computed mask and simulation results are shown to illustrate
effectiveness of ILT-generated SRAF features.
An implementation of inverse lithography technology is studied with special attention to
illustrating and analyzing the placement, accuracy, and efficacy of subresolution assist elements.
One-dimensional placement through pitch is characterized, and 2D capability is demonstrated for
repeated patterns. Differences between the methods of mask preparation afforded by this system
as compared to current practices are described.
Inverse lithography technology (ILT) was studied during process development for four layers from memory semiconductor designs. This paper describes techniques used in each of the layers. So as to demonstrate this technology in a wide range of semiconductor patterns, we show results from all four layers. Polysilicon was chosen to demonstrate the selection of exposure/defocus (ED) points for constraining the inversion. Marking process window boundaries during a mask creation run was demonstrated on a contact hole layer. With a deep trench layer, mask constraints were varied and write times studied. Lastly, wafer SEM images were collected for an active layer to explore image fidelity though focus and CD stability along a line.
Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD
measurements. However, these measurements are not comprehensive enough, limited to a very few layout features. It is desirable to confirm lithographic process window robustly, for all the cell design features of interest, to ensure full functionality of the cell. In this work, we propose for the first time to focus on the electrical deliverables after ILT pattern quality has been initially verified by SEM visual inspection. We designed an electrically measurable SRAM
structure for a 65 nm process, to extract device and interconnect parameters depending on the lithographic process conditions, as a means to compare pattern quality of the conventional mask creation technique, Optical Proximity Correction (OPC) with ILT. We present the drawn layout, the masks created by the two technologies, and the
corresponding image simulation and silicon pattern.
In this paper we present unintuitive patterns generated by inverse lithography technology. We show examples of contact hole masks designed with ILT that enjoy larger process windows than OPC. We also show variations in ILT-generated masks as the pitch of the contact hole array changes. In another example, we show poly masks designed for better process window to be substantially different from poly masks designed for better fidelity at nominal exposure-defocus (ED) condition. The mask with better fidelity has broken lines in comparison to the original layout. In a third example, we show deep trench mask patterns designed with ILT that, at first glance, bear no resemblance to the original layout, yet provide high fidelity in optical images. These patterns, although complex at first sight, can be generated in substantially simpler form with proper constraints without losing the spirit of ILT masks.
This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first test case, because SRAM bit-cells contain features which are challenging lithographically. Mask patterns generated from both conventional OPC and ILT were placed on the mask side-by-side. Mask manufacturability (including fracturing, writing time, inspection, and metrology) and wafer print performance of ILT were studied. The results demonstrated that ILT achieved better CD accuracy, produced substantially larger process window than conventional OPC, and met SMIC's 65nm process window requirements.