Shared shuttle runs are an important factor of the microelectronics business ecosystem, allowing fabless semiconductor
companies to access advanced processes and supporting the development of new tools and processes. We report on the
creation and progress of a shared shuttle program for access to advanced silicon photonics optoelectronic platforms that
we expect will create a similar environment for the field of integrated photonics.
Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production
CMOS electronics will enable new design paradigms for existing system architectures and open new
opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint,
weight, and power consumption of today's communication systems. While broadband analog system applications
represent a smaller volume market than that for digital data transmission, there are significant deployments of analog
electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block
in optical analog signal processing and also could have significant applications in digital communication systems.
Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma
dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges
and opportunities for analog signal processing since the index and
propagation loss change within the waveguide during
modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques
for optical modulation.
Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate
complimentary materials and process sequences required for high index contrast photonic components all within a single
CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits
at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the
Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems,
Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the
latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit
Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical
tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode
photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer
application. This presentation will review the latest advances of the passive and active photonic devices developed and
the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for
optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.
The complete integration of photonic devices into a CMOS process flow will enable low cost photonic functionality
within electronic circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, Cornell
University, and Applied Wave Research are participating in a high payoff research and development program for the
Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and
design tools necessary to fabricate an application specific, electronic-photonic integrated circuit (AS-EPIC). The first
phase of the program was dedicated to photonics device designs, CMOS process flow integration, and basic electronic
functionality. We will present the latest results on the performance of waveguide integrated detectors, and tunable
The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.
Acid catalyzed photoresists have been examined for exposure using the Helios compact synchrotron x-ray source at the IBM Advanced Lithography Facility. A fundamental challenge with these photoresists is the sensitivity to contamination from the environment. This study attempts to optimize a new type of Environmentally Stable Chemically Amplified Photoresist (ESCAP) developed by IBM Almaden Research Center. A key feature of this new resist is that it does not require an extra polymer topcoat to seal out airborne contaminants. The establishment of a base process and then the enhancement of exposure latitude was the main objective of the optimization. A 5 factor Taguchi optimization was designed to test the effects of post exposure bake (PEB) temperature, PEB time, post apply bake (PAB) temperature, PAB time and develop time. Sixteen wafers were utilized to explore 3 levels for each factor. Twenty-four additional wafers were run using the optimized process with slight variations. These were split into 3 runs for an estimate of noise. The second optimization used 4 factors with 3 interactions. The 200, 300, and 500 nm isolated line structures were examined. A test for maximum photospeed pointed to the same optimum region for latitude as well as sensitivity. Across all conditions a 5X change in dose for linewidth was shown while the exposure latitude for the 500 nm varied from 21 to 54%. The slopes fit to the subsequent plots ranged from 2 - 6 nm/mJ. The PEB latitude was seen to be 10 - 14 nm/ degree(s)C.
The synchrotron x ray lithography (XRL) project described was conducted as a learning and feasibility vehicle for gate level lithography in support of IBM's most advanced CMOS logic programs. An electrically probable multilevel lithography test site was developed and characterized to exercise critical design, mask manufacture, alignment, exposure, and metrology issues in the 150 - 350 nm linewidth range. A fully capped silicided polysilicon gate stack was chosen for the electrical measurements in order to develop and demonstrate the XRL and related reactive ion etch process on a realistic, product-like substrate. This paper addresses test site design issues, elaborates on the mask manufacturing process, and presents SEM and electrical data from wafers processed at IBM's Advanced Semiconductor Technology Center. The data presented demonstrate the feasibility of supporting early device development and process integration with XRL and highlight the need for high resolution, defect free, proximity corrected masks to fully exploit the capabilities of x ray lithography.
Acid catalyzed positive tone APEX photoresist has been examined for exposure using the Helios compact synchrotron x-ray source at the IBM Advanced Lithography Facility (ALF) in East Fishkill, New York. A four factor Taguchi optimization was implemented to test the effects of post exposure bake (PEB) temperature, PEB time, post apply bake (PAB) and develop time. The experiment was split into two tests; one for maximum process latitude and the other for attaining the target critical dimension (CD) of 350 nm. CD line widths were measured in resist using a top down scanning electron microscopy. The experimental analysis of variance indicated that 79% of the CD variation could be attributed to the PEB (temperature + time) and 12% from the PAB temperature/develop time interaction. Both tests converged on the same process conditions for maximum process latitude and target CD. These parameters reduced the thermal dose (PEB) in exchange for higher x-ray exposure. Line width uniformity data across 8' wafers will be shown for 200 nm structures and some additional results down to 125 nm using a 40 micrometers gap. Thermal infrared analysis of PEB hot plate uniformity was shown to be within specification but sensitive to backside wafer contamination. A novel 'net dose' exposure wedge which is built on the x-ray mask provided a record of the combined PEB/x-ray dose and did track with the thermal IR data.